597 lines
13 KiB
C
597 lines
13 KiB
C
/*
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* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <drivers/st/etzpc.h>
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#include <drivers/st/stm32_gpio.h>
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#include <platform_def.h>
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#include <stm32mp_shared_resources.h>
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/*
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* Once one starts to get the resource registering state, one cannot register
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* new resources. This ensures resource state cannot change.
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*/
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static bool registering_locked;
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/*
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* Shared peripherals and resources registration
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*
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* Each resource assignation is stored in a table. The state defaults
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* to PERIPH_UNREGISTERED if the resource is not explicitly assigned.
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*
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* Resource driver that as not embedded (a.k.a their related CFG_xxx build
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* directive is disabled) are assigned to the non-secure world.
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*
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* Each pin of the GPIOZ bank can be secure or non-secure.
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*
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* It is the platform responsibility the ensure resource assignation
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* matches the access permission firewalls configuration.
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*/
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enum shres_state {
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SHRES_UNREGISTERED = 0,
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SHRES_SECURE,
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SHRES_NON_SECURE,
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};
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/* Force uint8_t array for array of enum shres_state for size considerations */
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static uint8_t shres_state[STM32MP1_SHRES_COUNT];
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static const char *shres2str_id_tbl[STM32MP1_SHRES_COUNT] __unused = {
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[STM32MP1_SHRES_GPIOZ(0)] = "GPIOZ0",
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[STM32MP1_SHRES_GPIOZ(1)] = "GPIOZ1",
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[STM32MP1_SHRES_GPIOZ(2)] = "GPIOZ2",
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[STM32MP1_SHRES_GPIOZ(3)] = "GPIOZ3",
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[STM32MP1_SHRES_GPIOZ(4)] = "GPIOZ4",
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[STM32MP1_SHRES_GPIOZ(5)] = "GPIOZ5",
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[STM32MP1_SHRES_GPIOZ(6)] = "GPIOZ6",
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[STM32MP1_SHRES_GPIOZ(7)] = "GPIOZ7",
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[STM32MP1_SHRES_IWDG1] = "IWDG1",
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[STM32MP1_SHRES_USART1] = "USART1",
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[STM32MP1_SHRES_SPI6] = "SPI6",
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[STM32MP1_SHRES_I2C4] = "I2C4",
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[STM32MP1_SHRES_RNG1] = "RNG1",
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[STM32MP1_SHRES_HASH1] = "HASH1",
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[STM32MP1_SHRES_CRYP1] = "CRYP1",
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[STM32MP1_SHRES_I2C6] = "I2C6",
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[STM32MP1_SHRES_RTC] = "RTC",
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[STM32MP1_SHRES_MCU] = "MCU",
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[STM32MP1_SHRES_MDMA] = "MDMA",
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[STM32MP1_SHRES_PLL3] = "PLL3",
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};
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static const char __unused *shres2str_id(enum stm32mp_shres id)
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{
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assert(id < ARRAY_SIZE(shres2str_id_tbl));
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return shres2str_id_tbl[id];
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}
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static const char __unused *shres2str_state_tbl[] = {
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[SHRES_UNREGISTERED] = "unregistered",
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[SHRES_NON_SECURE] = "non-secure",
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[SHRES_SECURE] = "secure",
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};
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static const char __unused *shres2str_state(unsigned int state)
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{
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assert(state < ARRAY_SIZE(shres2str_state_tbl));
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return shres2str_state_tbl[state];
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}
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/* Get resource state: these accesses lock the registering support */
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static void lock_registering(void)
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{
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registering_locked = true;
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}
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static bool periph_is_non_secure(enum stm32mp_shres id)
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{
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lock_registering();
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return (shres_state[id] == SHRES_NON_SECURE) ||
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(shres_state[id] == SHRES_UNREGISTERED);
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}
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static bool periph_is_secure(enum stm32mp_shres id)
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{
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return !periph_is_non_secure(id);
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}
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/* GPIOZ pin count is saved in RAM to prevent parsing FDT several times */
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static int8_t gpioz_nbpin = -1;
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static unsigned int get_gpio_nbpin(unsigned int bank)
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{
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if (bank != GPIO_BANK_Z) {
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int count = fdt_get_gpio_bank_pin_count(bank);
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assert((count >= 0) && ((unsigned int)count <= (GPIO_PIN_MAX + 1)));
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return (unsigned int)count;
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}
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if (gpioz_nbpin < 0) {
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int count = fdt_get_gpio_bank_pin_count(GPIO_BANK_Z);
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assert((count == 0) || (count == STM32MP_GPIOZ_PIN_MAX_COUNT));
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gpioz_nbpin = count;
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}
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return (unsigned int)gpioz_nbpin;
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}
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static unsigned int get_gpioz_nbpin(void)
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{
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return get_gpio_nbpin(GPIO_BANK_Z);
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}
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static void register_periph(enum stm32mp_shres id, unsigned int state)
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{
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assert((id < STM32MP1_SHRES_COUNT) &&
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((state == SHRES_SECURE) || (state == SHRES_NON_SECURE)));
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if (registering_locked) {
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if (shres_state[id] == state) {
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return;
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}
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panic();
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}
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if ((shres_state[id] != SHRES_UNREGISTERED) &&
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(shres_state[id] != state)) {
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VERBOSE("Cannot change %s from %s to %s\n",
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shres2str_id(id),
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shres2str_state(shres_state[id]),
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shres2str_state(state));
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panic();
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}
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if (shres_state[id] == SHRES_UNREGISTERED) {
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VERBOSE("Register %s as %s\n",
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shres2str_id(id), shres2str_state(state));
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}
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if ((id >= STM32MP1_SHRES_GPIOZ(0)) &&
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(id <= STM32MP1_SHRES_GPIOZ(7)) &&
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((unsigned int)(id - STM32MP1_SHRES_GPIOZ(0)) >= get_gpioz_nbpin())) {
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ERROR("Invalid GPIO pin %d, %u pin(s) available\n",
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(int)(id - STM32MP1_SHRES_GPIOZ(0)), get_gpioz_nbpin());
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panic();
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}
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shres_state[id] = (uint8_t)state;
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/* Explore clock tree to lock dependencies */
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if (state == SHRES_SECURE) {
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enum stm32mp_shres clock_res_id;
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switch (id) {
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case STM32MP1_SHRES_GPIOZ(0):
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case STM32MP1_SHRES_GPIOZ(1):
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case STM32MP1_SHRES_GPIOZ(2):
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case STM32MP1_SHRES_GPIOZ(3):
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case STM32MP1_SHRES_GPIOZ(4):
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case STM32MP1_SHRES_GPIOZ(5):
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case STM32MP1_SHRES_GPIOZ(6):
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case STM32MP1_SHRES_GPIOZ(7):
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clock_res_id = GPIOZ;
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break;
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case STM32MP1_SHRES_IWDG1:
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clock_res_id = IWDG1;
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break;
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case STM32MP1_SHRES_USART1:
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clock_res_id = USART1_K;
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break;
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case STM32MP1_SHRES_SPI6:
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clock_res_id = SPI6_K;
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break;
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case STM32MP1_SHRES_I2C4:
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clock_res_id = I2C4_K;
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break;
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case STM32MP1_SHRES_RNG1:
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clock_res_id = RNG1_K;
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break;
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case STM32MP1_SHRES_HASH1:
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clock_res_id = HASH1;
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break;
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case STM32MP1_SHRES_CRYP1:
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clock_res_id = CRYP1;
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break;
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case STM32MP1_SHRES_I2C6:
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clock_res_id = I2C6_K;
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break;
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case STM32MP1_SHRES_RTC:
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clock_res_id = RTC;
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break;
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default:
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/* No clock resource dependency */
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return;
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}
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stm32mp1_register_clock_parents_secure(clock_res_id);
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}
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}
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/* Register resource by ID */
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void stm32mp_register_secure_periph(enum stm32mp_shres id)
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{
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register_periph(id, SHRES_SECURE);
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}
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void stm32mp_register_non_secure_periph(enum stm32mp_shres id)
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{
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register_periph(id, SHRES_NON_SECURE);
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}
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static void register_periph_iomem(uintptr_t base, unsigned int state)
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{
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enum stm32mp_shres id;
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switch (base) {
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case CRYP1_BASE:
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id = STM32MP1_SHRES_CRYP1;
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break;
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case HASH1_BASE:
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id = STM32MP1_SHRES_HASH1;
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break;
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case I2C4_BASE:
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id = STM32MP1_SHRES_I2C4;
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break;
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case I2C6_BASE:
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id = STM32MP1_SHRES_I2C6;
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break;
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case IWDG1_BASE:
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id = STM32MP1_SHRES_IWDG1;
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break;
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case RNG1_BASE:
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id = STM32MP1_SHRES_RNG1;
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break;
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case RTC_BASE:
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id = STM32MP1_SHRES_RTC;
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break;
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case SPI6_BASE:
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id = STM32MP1_SHRES_SPI6;
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break;
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case USART1_BASE:
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id = STM32MP1_SHRES_USART1;
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break;
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case GPIOA_BASE:
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case GPIOB_BASE:
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case GPIOC_BASE:
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case GPIOD_BASE:
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case GPIOE_BASE:
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case GPIOF_BASE:
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case GPIOG_BASE:
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case GPIOH_BASE:
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case GPIOI_BASE:
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case GPIOJ_BASE:
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case GPIOK_BASE:
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case USART2_BASE:
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case USART3_BASE:
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case UART4_BASE:
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case UART5_BASE:
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case USART6_BASE:
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case UART7_BASE:
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case UART8_BASE:
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case IWDG2_BASE:
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/* Allow drivers to register some non-secure resources */
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VERBOSE("IO for non-secure resource 0x%x\n",
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(unsigned int)base);
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if (state != SHRES_NON_SECURE) {
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panic();
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}
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return;
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default:
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panic();
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}
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register_periph(id, state);
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}
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void stm32mp_register_secure_periph_iomem(uintptr_t base)
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{
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register_periph_iomem(base, SHRES_SECURE);
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}
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void stm32mp_register_non_secure_periph_iomem(uintptr_t base)
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{
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register_periph_iomem(base, SHRES_NON_SECURE);
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}
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void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin)
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{
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switch (bank) {
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case GPIO_BANK_Z:
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register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_SECURE);
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break;
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default:
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ERROR("GPIO bank %u cannot be secured\n", bank);
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panic();
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}
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}
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void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin)
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{
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switch (bank) {
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case GPIO_BANK_Z:
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register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_NON_SECURE);
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break;
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default:
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break;
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}
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}
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static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
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{
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unsigned int non_secure = 0U;
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unsigned int i;
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lock_registering();
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if (bank != GPIO_BANK_Z) {
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return true;
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}
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for (i = 0U; i < get_gpioz_nbpin(); i++) {
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if (periph_is_non_secure(STM32MP1_SHRES_GPIOZ(i))) {
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non_secure++;
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}
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}
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return non_secure == get_gpioz_nbpin();
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}
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static bool stm32mp_gpio_bank_is_secure(unsigned int bank)
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{
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unsigned int secure = 0U;
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unsigned int i;
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lock_registering();
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if (bank != GPIO_BANK_Z) {
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return false;
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}
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for (i = 0U; i < get_gpioz_nbpin(); i++) {
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if (periph_is_secure(STM32MP1_SHRES_GPIOZ(i))) {
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secure++;
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}
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}
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return secure == get_gpioz_nbpin();
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}
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
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{
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enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
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switch (clock_id) {
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case CK_CSI:
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case CK_HSE:
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case CK_HSE_DIV2:
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case CK_HSI:
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case CK_LSE:
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case CK_LSI:
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case PLL1_P:
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case PLL1_Q:
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case PLL1_R:
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case PLL2_P:
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case PLL2_Q:
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case PLL2_R:
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case PLL3_P:
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case PLL3_Q:
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case PLL3_R:
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case RTCAPB:
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return true;
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case GPIOZ:
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/* Allow clock access if at least one pin is non-secure */
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return !stm32mp_gpio_bank_is_secure(GPIO_BANK_Z);
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case CRYP1:
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shres_id = STM32MP1_SHRES_CRYP1;
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break;
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case HASH1:
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shres_id = STM32MP1_SHRES_HASH1;
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break;
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case I2C4_K:
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shres_id = STM32MP1_SHRES_I2C4;
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break;
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case I2C6_K:
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shres_id = STM32MP1_SHRES_I2C6;
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break;
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case IWDG1:
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shres_id = STM32MP1_SHRES_IWDG1;
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break;
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case RNG1_K:
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shres_id = STM32MP1_SHRES_RNG1;
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break;
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case RTC:
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shres_id = STM32MP1_SHRES_RTC;
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break;
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case SPI6_K:
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shres_id = STM32MP1_SHRES_SPI6;
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break;
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case USART1_K:
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shres_id = STM32MP1_SHRES_USART1;
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break;
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default:
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return false;
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}
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return periph_is_non_secure(shres_id);
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}
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bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
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{
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enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
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switch (reset_id) {
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case CRYP1_R:
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shres_id = STM32MP1_SHRES_CRYP1;
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break;
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case GPIOZ_R:
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/* GPIOZ reset mandates all pins are non-secure */
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return stm32mp_gpio_bank_is_non_secure(GPIO_BANK_Z);
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case HASH1_R:
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shres_id = STM32MP1_SHRES_HASH1;
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break;
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case I2C4_R:
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shres_id = STM32MP1_SHRES_I2C4;
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break;
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case I2C6_R:
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shres_id = STM32MP1_SHRES_I2C6;
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break;
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case MCU_R:
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shres_id = STM32MP1_SHRES_MCU;
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break;
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case MDMA_R:
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shres_id = STM32MP1_SHRES_MDMA;
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break;
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case RNG1_R:
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shres_id = STM32MP1_SHRES_RNG1;
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break;
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case SPI6_R:
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shres_id = STM32MP1_SHRES_SPI6;
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break;
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case USART1_R:
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shres_id = STM32MP1_SHRES_USART1;
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break;
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default:
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return false;
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}
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return periph_is_non_secure(shres_id);
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}
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static bool mckprot_protects_periph(enum stm32mp_shres id)
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{
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switch (id) {
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case STM32MP1_SHRES_MCU:
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case STM32MP1_SHRES_PLL3:
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return true;
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default:
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return false;
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}
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}
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/* ETZPC configuration at drivers initialization completion */
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static enum etzpc_decprot_attributes shres2decprot_attr(enum stm32mp_shres id)
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{
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assert((id < STM32MP1_SHRES_GPIOZ(0)) ||
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(id > STM32MP1_SHRES_GPIOZ(7)));
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if (periph_is_non_secure(id)) {
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return ETZPC_DECPROT_NS_RW;
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}
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return ETZPC_DECPROT_S_RW;
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}
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static void set_etzpc_secure_configuration(void)
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{
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/* Some system peripherals shall be secure */
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etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW);
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etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW);
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etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID,
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ETZPC_DECPROT_NS_R_S_W);
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etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID,
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ETZPC_DECPROT_NS_R_S_W);
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/* Configure ETZPC with peripheral registering */
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etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID,
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shres2decprot_attr(STM32MP1_SHRES_CRYP1));
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etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID,
|
|
shres2decprot_attr(STM32MP1_SHRES_HASH1));
|
|
etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID,
|
|
shres2decprot_attr(STM32MP1_SHRES_I2C4));
|
|
etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID,
|
|
shres2decprot_attr(STM32MP1_SHRES_I2C6));
|
|
etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID,
|
|
shres2decprot_attr(STM32MP1_SHRES_IWDG1));
|
|
etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID,
|
|
shres2decprot_attr(STM32MP1_SHRES_RNG1));
|
|
etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID,
|
|
shres2decprot_attr(STM32MP1_SHRES_USART1));
|
|
etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID,
|
|
shres2decprot_attr(STM32MP1_SHRES_SPI6));
|
|
}
|
|
|
|
static void check_rcc_secure_configuration(void)
|
|
{
|
|
uint32_t n;
|
|
uint32_t error = 0U;
|
|
bool mckprot = stm32mp1_rcc_is_mckprot();
|
|
bool secure = stm32mp1_rcc_is_secure();
|
|
|
|
for (n = 0U; n < ARRAY_SIZE(shres_state); n++) {
|
|
if (shres_state[n] != SHRES_SECURE) {
|
|
continue;
|
|
}
|
|
|
|
if (!secure || (mckprot_protects_periph(n) && (!mckprot))) {
|
|
ERROR("RCC %s MCKPROT %s and %s secure\n",
|
|
secure ? "secure" : "non-secure",
|
|
mckprot ? "set" : "not set",
|
|
shres2str_id(n));
|
|
error++;
|
|
}
|
|
}
|
|
|
|
if (error != 0U) {
|
|
panic();
|
|
}
|
|
}
|
|
|
|
static void set_gpio_secure_configuration(void)
|
|
{
|
|
uint32_t pin;
|
|
|
|
for (pin = 0U; pin < get_gpioz_nbpin(); pin++) {
|
|
bool secure_state = periph_is_secure(STM32MP1_SHRES_GPIOZ(pin));
|
|
|
|
set_gpio_secure_cfg(GPIO_BANK_Z, pin, secure_state);
|
|
}
|
|
}
|
|
|
|
static void print_shared_resources_state(void)
|
|
{
|
|
unsigned int id;
|
|
|
|
for (id = 0U; id < STM32MP1_SHRES_COUNT; id++) {
|
|
switch (shres_state[id]) {
|
|
case SHRES_SECURE:
|
|
INFO("stm32mp1 %s is secure\n", shres2str_id(id));
|
|
break;
|
|
case SHRES_NON_SECURE:
|
|
case SHRES_UNREGISTERED:
|
|
VERBOSE("stm32mp %s is non-secure\n", shres2str_id(id));
|
|
break;
|
|
default:
|
|
VERBOSE("stm32mp %s is invalid\n", shres2str_id(id));
|
|
panic();
|
|
}
|
|
}
|
|
}
|
|
|
|
void stm32mp_lock_periph_registering(void)
|
|
{
|
|
registering_locked = true;
|
|
|
|
print_shared_resources_state();
|
|
|
|
check_rcc_secure_configuration();
|
|
set_etzpc_secure_configuration();
|
|
set_gpio_secure_configuration();
|
|
}
|