64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/*
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* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOCFPGA_FCS_H
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#define SOCFPGA_FCS_H
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/* FCS Definitions */
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#define FCS_RANDOM_WORD_SIZE 8U
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#define FCS_PROV_DATA_WORD_SIZE 44U
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#define FCS_SHA384_WORD_SIZE 12U
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#define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U)
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#define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U)
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#define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U)
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#define FCS_MODE_DECRYPT 0x0
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#define FCS_MODE_ENCRYPT 0x1
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#define FCS_ENCRYPTION_DATA_0 0x10100
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#define FCS_DECRYPTION_DATA_0 0x10102
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#define FCS_OWNER_ID_OFFSET 0xC
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/* FCS Payload Structure */
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typedef struct fcs_encrypt_payload_t {
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uint32_t first_word;
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uint32_t src_addr;
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uint32_t src_size;
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uint32_t dst_addr;
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uint32_t dst_size;
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} fcs_encrypt_payload;
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typedef struct fcs_decrypt_payload_t {
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uint32_t first_word;
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uint32_t owner_id[2];
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uint32_t src_addr;
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uint32_t src_size;
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uint32_t dst_addr;
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uint32_t dst_size;
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} fcs_decrypt_payload;
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/* Functions Definitions */
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uint32_t intel_fcs_random_number_gen(uint64_t addr, uint64_t *ret_size,
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uint32_t *mbox_error);
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uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
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uint32_t *send_id);
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uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
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uint32_t intel_fcs_encryption(uint32_t src_addr, uint32_t src_size,
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uint32_t dst_addr, uint32_t dst_size,
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uint32_t *send_id);
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uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size,
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uint32_t dst_addr, uint32_t dst_size,
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uint32_t *send_id);
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uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
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uint32_t *mbox_error);
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#endif /* SOCFPGA_FCS_H */
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