Pali Rohár a4d35ff381 feat(plat/marvell/a3k): add north and south bridge reset registers ... These registers make it is possible to do external resets of A3700 peripherals. Most peripherals are reset by clearing a particular bit, but some need setting the bit. Reflect this via "_N" suffix in macro names. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc		2021-12-02 17:37:58 +01:00
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a3700_plat_def.h	feat(plat/marvell/a3k): add north and south bridge reset registers	2021-12-02 17:37:58 +01:00
a3700_pm.h	plat: marvell: armada: a3k: support doing system reset via CM3 secure coprocessor	2021-01-05 14:01:51 +01:00
ddr_info.h	plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs	2020-06-18 20:57:45 +02:00
dram_win.h	plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs	2020-06-18 20:57:45 +02:00
io_addr_dec.h	plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs	2020-06-18 20:57:45 +02:00
plat_macros.S	plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs	2020-06-18 20:57:45 +02:00
platform_def.h	fix(plat/marvell/a3720/uart): fix UART parent clock rate determination	2021-06-02 14:19:52 +01:00