80 lines
1.6 KiB
C
80 lines
1.6 KiB
C
/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <mmio.h>
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#include <mt_cpu_pm_mbox.h>
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#include <platform_def.h>
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#include <sspm_reg.h>
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#define MCUPM_MBOX_3_BASE (MTK_MCUPM_SRAM_BASE + 0xFCE0)
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#define _sspm_mbox_write(id, val) \
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mmio_write_32(SSPM_MBOX_3_BASE + 4 * (id), val)
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#define _sspm_mbox_read(id) \
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mmio_read_32(SSPM_MBOX_3_BASE + 4 * (id))
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#define _mcupm_mbox_write(id, val) \
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mmio_write_32(MCUPM_MBOX_3_BASE + 4 * (id), val)
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#define _mcupm_mbox_read(id) \
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mmio_read_32(MCUPM_MBOX_3_BASE + 4 * (id))
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#define MCUPM_MBOX_OFFSET_PDN (0x0C55FDA8)
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#define MCUPM_POWER_DOWN (0x4D50444E)
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void mtk_set_sspm_lp_cmd(void *buf, unsigned int size)
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{
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unsigned int *p = (unsigned int *)buf;
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int i;
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for (i = 0; i < size; i++) {
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_sspm_mbox_write(SSPM_MBOX_SPM_CMD + i, p[i]);
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}
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}
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void mtk_clr_sspm_lp_cmd(unsigned int size)
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{
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int i;
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for (i = 0; i < size; i++) {
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_sspm_mbox_write(SSPM_MBOX_SPM_CMD + i, 0);
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}
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}
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void mtk_set_cpu_pm_pll_mode(unsigned int mode)
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{
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if (mode < NF_MCUPM_ARMPLL_MODE) {
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_mcupm_mbox_write(MCUPM_MBOX_ARMPLL_MODE, mode);
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}
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}
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int mtk_get_cpu_pm_pll_mode(void)
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{
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return _mcupm_mbox_read(MCUPM_MBOX_ARMPLL_MODE);
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}
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void mtk_set_cpu_pm_buck_mode(unsigned int mode)
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{
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if (mode < NF_MCUPM_BUCK_MODE) {
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_mcupm_mbox_write(MCUPM_MBOX_BUCK_MODE, mode);
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}
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}
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int mtk_get_cpu_pm_buck_mode(void)
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{
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return _mcupm_mbox_read(MCUPM_MBOX_BUCK_MODE);
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}
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void mtk_set_cpu_pm_preffered_cpu(unsigned int cpuid)
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{
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return _mcupm_mbox_read(MCUPM_MBOX_WAKEUP_CPU);
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}
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int mtk_set_cpu_pm_mbox_addr(uint64_t phy_addr)
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{
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return 0;
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}
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