136 lines
3.6 KiB
C
136 lines
3.6 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common_def.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <platform_def.h>
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#include <platform.h>
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#include <sp_res_desc.h>
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#include <string.h>
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#include <xlat_tables_v2.h>
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#include "spm_private.h"
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#include "spm_shim_private.h"
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/* Setup context of the Secure Partition */
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void spm_sp_setup(sp_context_t *sp_ctx)
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{
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cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
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/*
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* Initialize CPU context
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* ----------------------
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*/
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entry_point_info_t ep_info = {0};
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SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
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/* Setup entrypoint and SPSR */
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ep_info.pc = sp_ctx->rd.attribute.entrypoint;
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ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
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/*
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* X0: Unused (MBZ).
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* X1: Unused (MBZ).
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* X2: cookie value (Implementation Defined)
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* X3: cookie value (Implementation Defined)
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* X4 to X7 = 0
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*/
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ep_info.args.arg0 = 0;
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ep_info.args.arg1 = 0;
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ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
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ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
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cm_setup_context(ctx, &ep_info);
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/*
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* Setup translation tables
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* ------------------------
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*/
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sp_map_memory_regions(sp_ctx);
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/*
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* MMU-related registers
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* ---------------------
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*/
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xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle;
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uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
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setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table,
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xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
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EL1_EL0_REGIME);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1,
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mmu_cfg_params[MMU_CFG_MAIR]);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1,
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mmu_cfg_params[MMU_CFG_TCR]);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
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mmu_cfg_params[MMU_CFG_TTBR0]);
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/* Setup SCTLR_EL1 */
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u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
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sctlr_el1 |=
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/*SCTLR_EL1_RES1 |*/
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/* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
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SCTLR_UCI_BIT |
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/* RW regions at xlat regime EL1&0 are forced to be XN. */
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SCTLR_WXN_BIT |
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/* Don't trap to EL1 execution of WFI or WFE at EL0. */
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SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
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/* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
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SCTLR_UCT_BIT |
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/* Don't trap to EL1 execution of DZ ZVA at EL0. */
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SCTLR_DZE_BIT |
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/* Enable SP Alignment check for EL0 */
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SCTLR_SA0_BIT |
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/* Allow cacheable data and instr. accesses to normal memory. */
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SCTLR_C_BIT | SCTLR_I_BIT |
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/* Alignment fault checking enabled when at EL1 and EL0. */
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SCTLR_A_BIT |
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/* Enable MMU. */
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SCTLR_M_BIT
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;
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sctlr_el1 &= ~(
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/* Explicit data accesses at EL0 are little-endian. */
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SCTLR_E0E_BIT |
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/* Accesses to DAIF from EL0 are trapped to EL1. */
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SCTLR_UMA_BIT
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);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
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/*
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* Setup other system registers
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* ----------------------------
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*/
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/* Shim Exception Vector Base Address */
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
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SPM_SHIM_EXCEPTIONS_PTR);
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/*
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* FPEN: Allow the Secure Partition to access FP/SIMD registers.
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* Note that SPM will not do any saving/restoring of these registers on
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* behalf of the SP. This falls under the SP's responsibility.
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* TTA: Enable access to trace registers.
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* ZEN (v8.2): Trap SVE instructions and access to SVE registers.
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*/
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1,
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CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
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}
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