83 lines
1.8 KiB
ArmAsm
83 lines
1.8 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common_def.h>
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#include <memctrl_v2.h>
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#include <tegra_def.h>
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#define TEGRA186_SMMU_CTX_SIZE 0x420
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.globl tegra186_cpu_reset_handler
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/* CPU reset handler routine */
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func tegra186_cpu_reset_handler _align=4
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/*
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* The TZRAM loses state during System Suspend. We use this
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* information to decide if the reset handler is running after a
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* System Suspend. Resume from system suspend requires restoring
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* the entire state from TZDRAM to TZRAM.
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*/
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mov x0, #BL31_BASE
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ldr x0, [x0]
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cbnz x0, boot_cpu
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/* resume from system suspend */
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mov x0, #BL31_BASE
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adr x1, __tegra186_cpu_reset_handler_end
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adr x2, __tegra186_cpu_reset_handler_data
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ldr x2, [x2, #8]
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/* memcpy16 */
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m_loop16:
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cmp x2, #16
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b.lt m_loop1
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ldp x3, x4, [x1], #16
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stp x3, x4, [x0], #16
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sub x2, x2, #16
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b m_loop16
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/* copy byte per byte */
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m_loop1:
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cbz x2, boot_cpu
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ldrb w3, [x1], #1
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strb w3, [x0], #1
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subs x2, x2, #1
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b.ne m_loop1
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boot_cpu:
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adr x0, __tegra186_cpu_reset_handler_data
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ldr x0, [x0]
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br x0
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endfunc tegra186_cpu_reset_handler
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/*
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* Tegra186 reset data (offset 0x0 - 0x430)
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*
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* 0x000: secure world's entrypoint
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* 0x008: BL31 size (RO + RW)
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* 0x00C: SMMU context start
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* 0x42C: SMMU context end
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*/
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.align 4
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.type __tegra186_cpu_reset_handler_data, %object
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.globl __tegra186_cpu_reset_handler_data
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__tegra186_cpu_reset_handler_data:
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.quad tegra_secure_entrypoint
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.quad __BL31_END__ - BL31_BASE
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.globl __tegra186_smmu_context
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__tegra186_smmu_context:
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.rept TEGRA186_SMMU_CTX_SIZE
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.quad 0
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.endr
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.size __tegra186_cpu_reset_handler_data, \
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. - __tegra186_cpu_reset_handler_data
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.align 4
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.globl __tegra186_cpu_reset_handler_end
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__tegra186_cpu_reset_handler_end:
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