116 lines
3.8 KiB
ArmAsm
116 lines
3.8 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* ---------------------------------------------
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* Zero out the callee saved register to prevent
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* leakage of secure state into the normal world
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* during the first ERET after a cold/warm boot.
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* ---------------------------------------------
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*/
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.macro zero_callee_saved_regs
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mov x19, xzr
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mov x20, xzr
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mov x21, xzr
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mov x22, xzr
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mov x23, xzr
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mov x24, xzr
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mov x25, xzr
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mov x26, xzr
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mov x27, xzr
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mov x28, xzr
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mov x29, xzr
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.endm
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.macro switch_to_exception_stack reg1 reg2
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mov \reg1 , sp
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ldr \reg2, [\reg1, #CTX_EL3STATE_OFFSET + CTX_EXCEPTION_SP]
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mov sp, \reg2
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.endm
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/* -----------------------------------------------------
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* Handle SMC exceptions seperately from other sync.
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* exceptions.
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* -----------------------------------------------------
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*/
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.macro handle_sync_exception
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stp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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mrs x30, esr_el3
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ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x30, #EC_AARCH32_SMC
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b.eq smc_handler32
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cmp x30, #EC_AARCH64_SMC
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b.eq smc_handler64
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/* -----------------------------------------------------
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* The following code handles any synchronous exception
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* that is not an SMC. SP_EL3 is pointing to a context
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* structure where all the scratch registers are saved.
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* An exception stack is also retrieved from the context
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* Currently, a register dump is printed since BL31 does
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* not expect any such exceptions.
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* -----------------------------------------------------
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*/
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bl save_scratch_registers
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switch_to_exception_stack x0 x1
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/* Save the core_context pointer for handled faults */
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stp x0, xzr, [sp, #-0x10]!
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bl fault_handler
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ldp x0, xzr, [sp], #0x10
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mov sp, x0
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bl restore_scratch_registers
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ldp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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eret
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.endm
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/* -----------------------------------------------------
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* Use a platform defined mechanism to report an async.
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* exception.
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* -----------------------------------------------------
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*/
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.macro handle_async_exception type
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stp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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bl save_scratch_registers
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switch_to_exception_stack x0 x1
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/* Save the core_context pointer */
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stp x0, xzr, [sp, #-0x10]!
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mov x0, \type
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bl plat_report_exception
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ldp x0, xzr, [sp], #0x10
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mov sp, x0
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bl restore_scratch_registers
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ldp x30, xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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.endm
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