197 lines
7.5 KiB
C
197 lines
7.5 KiB
C
/*
|
|
* Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef STM32MP1_DDR_REGS_H
|
|
#define STM32MP1_DDR_REGS_H
|
|
|
|
#include <drivers/st/stm32mp_ddrctrl_regs.h>
|
|
#include <lib/utils_def.h>
|
|
|
|
/* DDR Physical Interface Control (DDRPHYC) registers*/
|
|
struct stm32mp_ddrphy {
|
|
uint32_t ridr; /* 0x00 R Revision Identification */
|
|
uint32_t pir; /* 0x04 R/W PHY Initialization */
|
|
uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
|
|
uint32_t pgsr; /* 0x0C PHY General Status */
|
|
uint32_t dllgcr; /* 0x10 R/W DLL General Control */
|
|
uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
|
|
uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
|
|
uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
|
|
uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
|
|
uint32_t aciocr; /* 0x24 AC I/O Configuration */
|
|
uint32_t dxccr; /* 0x28 DATX8 Common Configuration */
|
|
uint32_t dsgcr; /* 0x2C DDR System General Configuration */
|
|
uint32_t dcr; /* 0x30 DRAM Configuration */
|
|
uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */
|
|
uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */
|
|
uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */
|
|
uint32_t mr0; /* 0x40 Mode 0 */
|
|
uint32_t mr1; /* 0x44 Mode 1 */
|
|
uint32_t mr2; /* 0x48 Mode 2 */
|
|
uint32_t mr3; /* 0x4C Mode 3 */
|
|
uint32_t odtcr; /* 0x50 ODT Configuration */
|
|
uint32_t dtar; /* 0x54 data training address */
|
|
uint32_t dtdr0; /* 0x58 */
|
|
uint32_t dtdr1; /* 0x5c */
|
|
uint8_t res1[0x0c0 - 0x060]; /* 0x60 */
|
|
uint32_t dcuar; /* 0xc0 Address */
|
|
uint32_t dcudr; /* 0xc4 DCU Data */
|
|
uint32_t dcurr; /* 0xc8 DCU Run */
|
|
uint32_t dculr; /* 0xcc DCU Loop */
|
|
uint32_t dcugcr; /* 0xd0 DCU General Configuration */
|
|
uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */
|
|
uint32_t dcusr0; /* 0xd8 DCU Status 0 */
|
|
uint32_t dcusr1; /* 0xdc DCU Status 1 */
|
|
uint8_t res2[0x100 - 0xe0]; /* 0xe0 */
|
|
uint32_t bistrr; /* 0x100 BIST Run */
|
|
uint32_t bistmskr0; /* 0x104 BIST Mask 0 */
|
|
uint32_t bistmskr1; /* 0x108 BIST Mask 0 */
|
|
uint32_t bistwcr; /* 0x10c BIST Word Count */
|
|
uint32_t bistlsr; /* 0x110 BIST LFSR Seed */
|
|
uint32_t bistar0; /* 0x114 BIST Address 0 */
|
|
uint32_t bistar1; /* 0x118 BIST Address 1 */
|
|
uint32_t bistar2; /* 0x11c BIST Address 2 */
|
|
uint32_t bistupdr; /* 0x120 BIST User Data Pattern */
|
|
uint32_t bistgsr; /* 0x124 BIST General Status */
|
|
uint32_t bistwer; /* 0x128 BIST Word Error */
|
|
uint32_t bistber0; /* 0x12c BIST Bit Error 0 */
|
|
uint32_t bistber1; /* 0x130 BIST Bit Error 1 */
|
|
uint32_t bistber2; /* 0x134 BIST Bit Error 2 */
|
|
uint32_t bistwcsr; /* 0x138 BIST Word Count Status */
|
|
uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */
|
|
uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */
|
|
uint8_t res3[0x178 - 0x144]; /* 0x144 */
|
|
uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */
|
|
uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */
|
|
uint32_t zq0cr0; /* 0x180 zq 0 control 0 */
|
|
uint32_t zq0cr1; /* 0x184 zq 0 control 1 */
|
|
uint32_t zq0sr0; /* 0x188 zq 0 status 0 */
|
|
uint32_t zq0sr1; /* 0x18C zq 0 status 1 */
|
|
uint8_t res4[0x1C0 - 0x190]; /* 0x190 */
|
|
uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */
|
|
uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */
|
|
uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */
|
|
uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */
|
|
uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */
|
|
uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */
|
|
uint8_t res5[0x200 - 0x1d8]; /* 0x1d8 */
|
|
uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */
|
|
uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */
|
|
uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */
|
|
uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */
|
|
uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */
|
|
uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */
|
|
uint8_t res6[0x240 - 0x218]; /* 0x218 */
|
|
#if STM32MP_DDR_32BIT_INTERFACE
|
|
uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
|
|
uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */
|
|
uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */
|
|
uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */
|
|
uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */
|
|
uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */
|
|
uint8_t res7[0x280 - 0x258]; /* 0x258 */
|
|
uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */
|
|
uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */
|
|
uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */
|
|
uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */
|
|
uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */
|
|
uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */
|
|
#endif
|
|
} __packed;
|
|
|
|
/* DDR PHY registers offsets */
|
|
#define DDRPHYC_PIR 0x004
|
|
#define DDRPHYC_PGCR 0x008
|
|
#define DDRPHYC_PGSR 0x00C
|
|
#define DDRPHYC_DLLGCR 0x010
|
|
#define DDRPHYC_ACDLLCR 0x014
|
|
#define DDRPHYC_PTR0 0x018
|
|
#define DDRPHYC_ACIOCR 0x024
|
|
#define DDRPHYC_DXCCR 0x028
|
|
#define DDRPHYC_DSGCR 0x02C
|
|
#define DDRPHYC_ZQ0CR0 0x180
|
|
#define DDRPHYC_DX0GCR 0x1C0
|
|
#define DDRPHYC_DX0DLLCR 0x1CC
|
|
#define DDRPHYC_DX1GCR 0x200
|
|
#define DDRPHYC_DX1DLLCR 0x20C
|
|
#if STM32MP_DDR_32BIT_INTERFACE
|
|
#define DDRPHYC_DX2GCR 0x240
|
|
#define DDRPHYC_DX2DLLCR 0x24C
|
|
#define DDRPHYC_DX3GCR 0x280
|
|
#define DDRPHYC_DX3DLLCR 0x28C
|
|
#endif
|
|
|
|
/* DDR PHY Register fields */
|
|
#define DDRPHYC_PIR_INIT BIT(0)
|
|
#define DDRPHYC_PIR_DLLSRST BIT(1)
|
|
#define DDRPHYC_PIR_DLLLOCK BIT(2)
|
|
#define DDRPHYC_PIR_ZCAL BIT(3)
|
|
#define DDRPHYC_PIR_ITMSRST BIT(4)
|
|
#define DDRPHYC_PIR_DRAMRST BIT(5)
|
|
#define DDRPHYC_PIR_DRAMINIT BIT(6)
|
|
#define DDRPHYC_PIR_QSTRN BIT(7)
|
|
#define DDRPHYC_PIR_RVTRN BIT(8)
|
|
#define DDRPHYC_PIR_ICPC BIT(16)
|
|
#define DDRPHYC_PIR_ZCALBYP BIT(30)
|
|
#define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7)
|
|
|
|
#define DDRPHYC_PGCR_DFTCMP BIT(2)
|
|
#define DDRPHYC_PGCR_PDDISDX BIT(24)
|
|
#define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25)
|
|
|
|
#define DDRPHYC_PGSR_IDONE BIT(0)
|
|
#define DDRPHYC_PGSR_DTERR BIT(5)
|
|
#define DDRPHYC_PGSR_DTIERR BIT(6)
|
|
#define DDRPHYC_PGSR_DFTERR BIT(7)
|
|
#define DDRPHYC_PGSR_RVERR BIT(8)
|
|
#define DDRPHYC_PGSR_RVEIRR BIT(9)
|
|
|
|
#define DDRPHYC_DLLGCR_BPS200 BIT(23)
|
|
|
|
#define DDRPHYC_ACDLLCR_DLLSRST BIT(30)
|
|
#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
|
|
|
|
#define DDRPHYC_PTR0_TDLLSRST_OFFSET 0
|
|
#define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0)
|
|
#define DDRPHYC_PTR0_TDLLLOCK_OFFSET 6
|
|
#define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6)
|
|
#define DDRPHYC_PTR0_TITMSRST_OFFSET 18
|
|
#define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18)
|
|
|
|
#define DDRPHYC_ACIOCR_ACPDD BIT(3)
|
|
#define DDRPHYC_ACIOCR_ACPDR BIT(4)
|
|
#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8)
|
|
#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8)
|
|
#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11)
|
|
#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11)
|
|
#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18)
|
|
#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18)
|
|
#define DDRPHYC_ACIOCR_RSTPDD BIT(27)
|
|
#define DDRPHYC_ACIOCR_RSTPDR BIT(28)
|
|
|
|
#define DDRPHYC_DXCCR_DXPDD BIT(2)
|
|
#define DDRPHYC_DXCCR_DXPDR BIT(3)
|
|
|
|
#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16)
|
|
#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16)
|
|
#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20)
|
|
#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20)
|
|
#define DDRPHYC_DSGCR_NL2PD BIT(24)
|
|
|
|
#define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0)
|
|
#define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0
|
|
#define DDRPHYC_ZQ0CRN_ZDEN BIT(28)
|
|
#define DDRPHYC_ZQ0CRN_ZQPD BIT(31)
|
|
|
|
#define DDRPHYC_DXNGCR_DXEN BIT(0)
|
|
|
|
#define DDRPHYC_DXNDLLCR_DLLSRST BIT(30)
|
|
#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31)
|
|
#define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14)
|
|
#define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14
|
|
|
|
#endif /* STM32MP1_DDR_REGS_H */
|