168 lines
4.3 KiB
ArmAsm
168 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include "../fpga_private.h"
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#include <platform_def.h>
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.globl plat_get_my_entrypoint
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl platform_mem_init
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl plat_fpga_calc_core_pos
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/* -----------------------------------------------------------------------
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* Indicate a cold boot for every CPU - warm boot is unsupported for the
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* holding pen PSCI implementation.
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* -----------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov x0, #0
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ret
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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* -----------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/*
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* Wait for the primary processor to initialise the .BSS segment
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* to avoid a race condition that would erase fpga_valid_mpids
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* if it is populated before the C runtime is ready.
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*
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* We cannot use the current spin-lock implementation until the
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* runtime is up and we should not rely on sevl/wfe instructions as
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* it is optional whether they are implemented or not, so we use
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* a global variable as lock and wait for the primary processor to
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* finish the C runtime bring-up.
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*/
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ldr w0, =C_RUNTIME_READY_KEY
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adrp x1, secondary_core_spinlock
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add x1, x1, :lo12:secondary_core_spinlock
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1:
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wfe
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ldr w2, [x1]
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cmp w2, w0
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b.ne 1b
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/* Prevent reordering of the store into fpga_valid_mpids below */
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dmb ish
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mov x10, x30
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bl plat_my_core_pos
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mov x30, x10
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adrp x4, fpga_valid_mpids
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add x4, x4, :lo12:fpga_valid_mpids
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mov x5, #VALID_MPID
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strb w5, [x4, x0]
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/*
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* Poll the CPU's hold entry until it indicates to jump
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* to the entrypoint address.
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*/
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adrp x1, hold_base
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add x1, x1, :lo12:hold_base
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poll_hold_entry:
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ldr x3, [x1, x0, LSL #PLAT_FPGA_HOLD_ENTRY_SHIFT]
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cmp x3, #PLAT_FPGA_HOLD_STATE_GO
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b.ne 1f
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adrp x2, fpga_sec_entrypoint
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add x2, x2, :lo12:fpga_sec_entrypoint
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ldr x3, [x2]
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br x3
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1:
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wfe
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b poll_hold_entry
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endfunc plat_secondary_cold_boot_setup
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/* -----------------------------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary cpu
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* -----------------------------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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mov_imm x1, MPIDR_AFFINITY_MASK
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and x0, x0, x1
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cmp x0, #FPGA_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func plat_my_core_pos
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ldr x1, =(MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT))
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mrs x0, mpidr_el1
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and x0, x0, x1
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b plat_fpga_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------------------------
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* unsigned int plat_fpga_calc_core_pos (uint32_t mpid)
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* Clobber registers: x0 to x5
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* -----------------------------------------------------------------------
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*/
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func plat_fpga_calc_core_pos
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/*
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* Check for MT bit in MPIDR, which may be either value for images
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* running on the FPGA.
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*
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* If not set, shift MPIDR to left to make it look as if in a
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* multi-threaded implementation.
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*
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*/
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tst x0, #MPIDR_MT_MASK
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lsl x3, x0, #MPIDR_AFFINITY_BITS
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csel x3, x3, x0, eq
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/* Extract individual affinity fields from MPIDR */
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ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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mov x4, #FPGA_MAX_CPUS_PER_CLUSTER
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mov x5, #FPGA_MAX_PE_PER_CPU
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/* Compute linear position */
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madd x1, x2, x4, x1
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madd x0, x1, x5, x0
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ret
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endfunc plat_fpga_calc_core_pos
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func plat_crash_console_init
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mov_imm x0, PLAT_FPGA_CRASH_UART_BASE
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b console_pl011_core_init
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endfunc plat_crash_console_init
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func plat_crash_console_putc
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mov_imm x1, PLAT_FPGA_CRASH_UART_BASE
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b console_pl011_core_putc
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov_imm x0, PLAT_FPGA_CRASH_UART_BASE
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b console_pl011_core_flush
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endfunc plat_crash_console_flush
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