154 lines
4.0 KiB
C
154 lines
4.0 KiB
C
/*
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* Copyright (c) 2016 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BRCM_DEF_H
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#define BRCM_DEF_H
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <plat/common/common_def.h>
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#include <platform_def.h>
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#define PLAT_PHY_ADDR_SPACE_SIZE BIT_64(32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE BIT_64(32)
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#define BL11_DAUTH_ID 0x796C51ab
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#define BL11_DAUTH_BASE BL11_RW_BASE
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/* We keep a table at the end of ROM for function pointers */
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#define ROM_TABLE_SIZE 32
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#define BL1_ROM_TABLE (BL1_RO_LIMIT - ROM_TABLE_SIZE)
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/*
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* The top 16MB of DRAM1 is configured as secure access only using the TZC
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* - SCP TZC DRAM: If present, DRAM reserved for SCP use
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* - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
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*/
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#define BRCM_TZC_DRAM1_SIZE ULL(0x01000000)
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#define BRCM_SCP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \
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BRCM_DRAM1_SIZE - \
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BRCM_SCP_TZC_DRAM1_SIZE)
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#define BRCM_SCP_TZC_DRAM1_SIZE PLAT_BRCM_SCP_TZC_DRAM1_SIZE
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#define BRCM_AP_TZC_DRAM1_BASE (BRCM_DRAM1_BASE + \
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BRCM_DRAM1_SIZE - \
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BRCM_TZC_DRAM1_SIZE)
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#define BRCM_AP_TZC_DRAM1_SIZE (BRCM_TZC_DRAM1_SIZE - \
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BRCM_SCP_TZC_DRAM1_SIZE)
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#define BRCM_NS_DRAM1_BASE BRCM_DRAM1_BASE
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#define BRCM_NS_DRAM1_SIZE (BRCM_DRAM1_SIZE - \
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BRCM_TZC_DRAM1_SIZE)
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#ifdef BRCM_SHARED_DRAM_BASE
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#define BRCM_NS_SHARED_DRAM_BASE BRCM_SHARED_DRAM_BASE
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#define BRCM_NS_SHARED_DRAM_SIZE BRCM_SHARED_DRAM_SIZE
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#endif
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#define BRCM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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BRCM_SHARED_RAM_BASE, \
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BRCM_SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define BRCM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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BRCM_NS_DRAM1_BASE, \
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BRCM_NS_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#ifdef BRCM_SHARED_DRAM_BASE
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#define BRCM_MAP_NS_SHARED_DRAM MAP_REGION_FLAT( \
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BRCM_NS_SHARED_DRAM_BASE, \
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BRCM_NS_SHARED_DRAM_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#endif
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#ifdef BRCM_EXT_SRAM_BASE
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#define BRCM_MAP_EXT_SRAM MAP_REGION_FLAT( \
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BRCM_EXT_SRAM_BASE, \
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BRCM_EXT_SRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#define BRCM_MAP_NAND_RO MAP_REGION_FLAT(NAND_BASE_ADDR,\
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NAND_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define BRCM_MAP_QSPI_RO MAP_REGION_FLAT(QSPI_BASE_ADDR,\
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QSPI_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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#define HSLS_REGION MAP_REGION_FLAT(HSLS_BASE_ADDR, \
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HSLS_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define CCN_REGION MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \
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CCN_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define GIC500_REGION MAP_REGION_FLAT(GIC500_BASE, \
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GIC500_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#ifdef PERIPH0_BASE
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#define PERIPH0_REGION MAP_REGION_FLAT(PERIPH0_BASE, \
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PERIPH0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#ifdef PERIPH1_BASE
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#define PERIPH1_REGION MAP_REGION_FLAT(PERIPH1_BASE, \
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PERIPH1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#ifdef PERIPH2_BASE
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#define PERIPH2_REGION MAP_REGION_FLAT(PERIPH2_BASE, \
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PERIPH2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#if BRCM_BL31_IN_DRAM
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#if IMAGE_BL2
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#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
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BL31_BASE, \
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PLAT_BRCM_MAX_BL31_SIZE,\
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MT_DEVICE | MT_RW | MT_SECURE)
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#else
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#define BRCM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
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BL31_BASE, \
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PLAT_BRCM_MAX_BL31_SIZE,\
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#endif
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#if defined(USB_BASE) && defined(DRIVER_USB_ENABLE)
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#define USB_REGION MAP_REGION_FLAT( \
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USB_BASE, \
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USB_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#ifdef USE_CRMU_SRAM
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#define CRMU_SRAM_REGION MAP_REGION_FLAT( \
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CRMU_SRAM_BASE, \
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CRMU_SRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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/*
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* The number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#if USE_COHERENT_MEM
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#define BRCM_BL_REGIONS 3
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#else
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#define BRCM_BL_REGIONS 2
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#endif
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#endif /* BRCM_DEF_H */
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