31 lines
798 B
Plaintext
31 lines
798 B
Plaintext
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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/* Platform Config */
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plat_arm_bl2 {
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compatible = "arm,tb_fw";
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hw_config_addr = <0x0 0x82000000>;
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hw_config_max_size = <0x01000000>;
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/* Disable authentication for development */
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disable_auth = <0x0>;
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/*
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* Load SoC and TOS firmware configs at the base of
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* non shared SRAM. The runtime checks ensure we don't
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* overlap BL2, BL31 or BL32. The NT firmware config
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* is loaded at base of DRAM.
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*/
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soc_fw_config_addr = <0x0 0x04001000>;
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soc_fw_config_max_size = <0x200>;
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tos_fw_config_addr = <0x0 0x04001200>;
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tos_fw_config_max_size = <0x200>;
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nt_fw_config_addr = <0x0 0x80000000>;
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nt_fw_config_max_size = <0x200>;
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};
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};
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