Varun Wadekar b0301467bc Workaround for CVE-2017-5715 on NVIDIA Denver CPUs ... Flush the indirect branch predictor and RSB on entry to EL3 by issuing a newly added instruction for Denver CPUs. Support for this operation can be determined by comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. Change-Id: Ief493cd85935bab3cfee0397e856db5101bc8011 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2018-05-15 15:53:50 -07:00
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aarch32	Fixup AArch32 errata printing framework	2018-02-22 15:19:52 +00:00
aarch64	Workaround for CVE-2017-5715 on NVIDIA Denver CPUs	2018-05-15 15:53:50 -07:00
cpu-ops.mk	Workaround for CVE-2017-5715 on Cortex A57 and A72	2018-01-11 10:26:15 +00:00
errata_report.c	Merge pull request #1228 from dp-arm/dp/cve_2017_5715	2018-01-25 00:06:50 +00:00