373 lines
10 KiB
C
373 lines
10 KiB
C
/*
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <common/debug.h>
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#include <lib/bakery_lock.h>
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#include <lib/extensions/ras.h>
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#include <lib/utils_def.h>
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#include <services/sdei.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <tegra194_ras_private.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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/*
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* ERR<n>FR bits[63:32], it indicates supported RAS errors which can be enabled
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* by setting corresponding bits in ERR<n>CTLR
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*/
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#define ERR_FR_EN_BITS_MASK 0xFFFFFFFF00000000ULL
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/* bakery lock for platform RAS handler. */
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static DEFINE_BAKERY_LOCK(ras_handler_lock);
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#define ras_lock() bakery_lock_get(&ras_handler_lock)
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#define ras_unlock() bakery_lock_release(&ras_handler_lock)
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/*
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* Function to handle an External Abort received at EL3.
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* This function is invoked by RAS framework.
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*/
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static void tegra194_ea_handler(unsigned int ea_reason, uint64_t syndrome,
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void *cookie, void *handle, uint64_t flags)
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{
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int32_t ret;
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ras_lock();
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ERROR("exception reason=%u syndrome=0x%llx on 0x%lx at EL3.\n",
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ea_reason, syndrome, read_mpidr_el1());
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/* Call RAS EA handler */
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ret = ras_ea_handler(ea_reason, syndrome, cookie, handle, flags);
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if (ret != 0) {
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ERROR("RAS error handled!\n");
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ret = sdei_dispatch_event(TEGRA_SDEI_EP_EVENT_0 +
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plat_my_core_pos());
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if (ret != 0)
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ERROR("sdei_dispatch_event returned %d\n", ret);
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} else {
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ERROR("Not a RAS error!\n");
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}
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ras_unlock();
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}
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/*
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* Function to enable all supported RAS error report.
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*
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* Uncorrected errors are set to report as External abort (SError)
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* Corrected errors are set to report as interrupt.
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*/
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void tegra194_ras_enable(void)
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{
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VERBOSE("%s\n", __func__);
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/* skip RAS enablement if not a silicon platform. */
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if (!tegra_platform_is_silicon()) {
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return;
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}
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/*
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* Iterate for each group(num_idx ERRSELRs starting from idx_start)
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* use normal for loop instead of for_each_err_record_info to get rid
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* of MISRA noise..
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*/
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for (uint32_t i = 0U; i < err_record_mappings.num_err_records; i++) {
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const struct err_record_info *info = &err_record_mappings.err_records[i];
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uint32_t idx_start = info->sysreg.idx_start;
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uint32_t num_idx = info->sysreg.num_idx;
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const struct ras_aux_data *aux_data = (const struct ras_aux_data *)info->aux_data;
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assert(aux_data != NULL);
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for (uint32_t j = 0; j < num_idx; j++) {
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/* ERR<n>CTLR register value. */
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uint64_t err_ctrl = 0ULL;
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/* all supported errors for this node. */
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uint64_t err_fr;
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/* uncorrectable errors */
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uint64_t uncorr_errs;
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/* correctable errors */
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uint64_t corr_errs;
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/*
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* Catch error if something wrong with the RAS aux data
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* record table.
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*/
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assert(aux_data[j].err_ctrl != NULL);
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/*
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* Write to ERRSELR_EL1 to select the RAS error node.
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* Always program this at first to select corresponding
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* RAS node before any other RAS register r/w.
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*/
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ser_sys_select_record(idx_start + j);
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err_fr = read_erxfr_el1() & ERR_FR_EN_BITS_MASK;
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uncorr_errs = aux_data[j].err_ctrl();
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corr_errs = ~uncorr_errs & err_fr;
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/* enable error reporting */
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ERR_CTLR_ENABLE_FIELD(err_ctrl, ED);
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/* enable SError reporting for uncorrectable errors */
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if ((uncorr_errs & err_fr) != 0ULL) {
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ERR_CTLR_ENABLE_FIELD(err_ctrl, UE);
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}
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/* generate interrupt for corrected errors. */
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if (corr_errs != 0ULL) {
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ERR_CTLR_ENABLE_FIELD(err_ctrl, CFI);
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}
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/* enable the supported errors */
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err_ctrl |= err_fr;
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VERBOSE("errselr_el1:0x%x, erxfr:0x%llx, err_ctrl:0x%llx\n",
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idx_start + j, err_fr, err_ctrl);
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/* enable specified errors, or set to 0 if no supported error */
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write_erxctlr_el1(err_ctrl);
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/*
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* Check if all the bit settings have been enabled to detect
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* uncorrected/corrected errors, if not assert.
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*/
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assert(read_erxctlr_el1() == err_ctrl);
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}
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}
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}
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/*
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* Function to clear RAS ERR<n>STATUS for corrected RAS error.
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* This function ignores any new RAS error signaled during clearing; it is not
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* multi-core safe(no ras_lock is taken to reduce overhead).
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*/
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void tegra194_ras_corrected_err_clear(void)
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{
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uint64_t clear_ce_status = 0ULL;
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ERR_STATUS_SET_FIELD(clear_ce_status, AV, 0x1UL);
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ERR_STATUS_SET_FIELD(clear_ce_status, V, 0x1UL);
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ERR_STATUS_SET_FIELD(clear_ce_status, OF, 0x1UL);
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ERR_STATUS_SET_FIELD(clear_ce_status, MV, 0x1UL);
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ERR_STATUS_SET_FIELD(clear_ce_status, CE, 0x3UL);
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for (uint32_t i = 0U; i < err_record_mappings.num_err_records; i++) {
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const struct err_record_info *info = &err_record_mappings.err_records[i];
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uint32_t idx_start = info->sysreg.idx_start;
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uint32_t num_idx = info->sysreg.num_idx;
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for (uint32_t j = 0U; j < num_idx; j++) {
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uint64_t status;
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uint32_t err_idx = idx_start + j;
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write_errselr_el1(err_idx);
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status = read_erxstatus_el1();
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if (ERR_STATUS_GET_FIELD(status, CE) != 0U) {
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write_erxstatus_el1(clear_ce_status);
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}
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}
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}
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}
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/* Function to probe an error from error record group. */
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static int32_t tegra194_ras_record_probe(const struct err_record_info *info,
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int *probe_data)
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{
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/* Skip probing if not a silicon platform */
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if (!tegra_platform_is_silicon()) {
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return 0;
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}
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return ser_probe_sysreg(info->sysreg.idx_start, info->sysreg.num_idx, probe_data);
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}
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/* Function to handle error from one given node */
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static int32_t tegra194_ras_node_handler(uint32_t errselr,
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const struct ras_error *errors, uint64_t status)
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{
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bool found = false;
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uint32_t ierr = (uint32_t)ERR_STATUS_GET_FIELD(status, IERR);
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uint32_t serr = (uint32_t)ERR_STATUS_GET_FIELD(status, SERR);
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/* not a valid error. */
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if (ERR_STATUS_GET_FIELD(status, V) == 0U) {
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return 0;
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}
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/* Print uncorrectable errror information. */
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if (ERR_STATUS_GET_FIELD(status, UE) != 0U) {
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/* IERR to error message */
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for (uint32_t i = 0; errors[i].error_msg != NULL; i++) {
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if (ierr == errors[i].error_code) {
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ERROR("ERRSELR_EL1:0x%x\n, IERR = %s(0x%x)\n",
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errselr, errors[i].error_msg,
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errors[i].error_code);
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found = true;
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break;
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}
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}
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if (!found) {
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ERROR("unknown uncorrectable eror, "
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"ERRSELR_EL1:0x%x, IERR: 0x%x\n", errselr, ierr);
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}
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ERROR("SERR = %s(0x%x)\n", ras_serr_to_str(serr), serr);
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} else {
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/* For corrected error, simply clear it. */
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VERBOSE("corrected RAS error is cleared: ERRSELR_EL1:0x%x, "
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"IERR:0x%x, SERR:0x%x\n", errselr, ierr, serr);
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}
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/* Write to clear reported errors. */
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write_erxstatus_el1(status);
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return 0;
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}
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/* Function to handle one error node from an error record group. */
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static int32_t tegra194_ras_record_handler(const struct err_record_info *info,
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int probe_data, const struct err_handler_data *const data __unused)
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{
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uint32_t num_idx = info->sysreg.num_idx;
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uint32_t idx_start = info->sysreg.idx_start;
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const struct ras_aux_data *aux_data = info->aux_data;
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const struct ras_error *errors;
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uint32_t offset;
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uint64_t status = 0ULL;
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VERBOSE("%s\n", __func__);
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assert(probe_data >= 0);
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assert((uint32_t)probe_data < num_idx);
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offset = (uint32_t)probe_data;
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errors = aux_data[offset].error_records;
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assert(errors != NULL);
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/* Write to ERRSELR_EL1 to select the error record */
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ser_sys_select_record(idx_start + offset);
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/* Retrieve status register from the error record */
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status = read_erxstatus_el1();
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return tegra194_ras_node_handler(idx_start + offset, errors, status);
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}
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/* Instantiate RAS nodes */
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PER_CORE_RAS_NODE_LIST(DEFINE_ONE_RAS_NODE)
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PER_CLUSTER_RAS_NODE_LIST(DEFINE_ONE_RAS_NODE)
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SCF_L3_BANK_RAS_NODE_LIST(DEFINE_ONE_RAS_NODE)
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CCPLEX_RAS_NODE_LIST(DEFINE_ONE_RAS_NODE)
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/* Instantiate RAS node groups */
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static struct ras_aux_data per_core_ras_group[] = {
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PER_CORE_RAS_GROUP_NODES
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};
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static struct ras_aux_data per_cluster_ras_group[] = {
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PER_CLUSTER_RAS_GROUP_NODES
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};
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static struct ras_aux_data scf_l3_ras_group[] = {
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SCF_L3_BANK_RAS_GROUP_NODES
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};
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static struct ras_aux_data ccplex_ras_group[] = {
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CCPLEX_RAS_GROUP_NODES
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};
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/*
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* We have same probe and handler for each error record group, use a macro to
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* simply the record definition.
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*/
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#define ADD_ONE_ERR_GROUP(errselr_start, group) \
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ERR_RECORD_SYSREG_V1((errselr_start), (uint32_t)ARRAY_SIZE((group)), \
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&tegra194_ras_record_probe, \
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&tegra194_ras_record_handler, (group))
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/* RAS error record group information */
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static struct err_record_info carmel_ras_records[] = {
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/*
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* Per core ras error records
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* ERRSELR starts from 0*256 + Logical_CPU_ID*16 + 0 to
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* 0*256 + Logical_CPU_ID*16 + 5 for each group.
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* 8 cores/groups, 6 * 8 nodes in total.
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*/
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ADD_ONE_ERR_GROUP(0x000, per_core_ras_group),
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ADD_ONE_ERR_GROUP(0x010, per_core_ras_group),
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ADD_ONE_ERR_GROUP(0x020, per_core_ras_group),
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ADD_ONE_ERR_GROUP(0x030, per_core_ras_group),
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ADD_ONE_ERR_GROUP(0x040, per_core_ras_group),
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ADD_ONE_ERR_GROUP(0x050, per_core_ras_group),
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ADD_ONE_ERR_GROUP(0x060, per_core_ras_group),
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ADD_ONE_ERR_GROUP(0x070, per_core_ras_group),
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/*
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* Per cluster ras error records
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* ERRSELR starts from 2*256 + Logical_Cluster_ID*16 + 0 to
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* 2*256 + Logical_Cluster_ID*16 + 3.
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* 4 clusters/groups, 3 * 4 nodes in total.
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*/
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ADD_ONE_ERR_GROUP(0x200, per_cluster_ras_group),
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ADD_ONE_ERR_GROUP(0x210, per_cluster_ras_group),
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ADD_ONE_ERR_GROUP(0x220, per_cluster_ras_group),
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ADD_ONE_ERR_GROUP(0x230, per_cluster_ras_group),
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/*
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* SCF L3_Bank ras error records
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* ERRSELR: 3*256 + L3_Bank_ID, L3_Bank_ID: 0-3
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* 1 groups, 4 nodes in total.
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*/
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ADD_ONE_ERR_GROUP(0x300, scf_l3_ras_group),
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/*
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* CCPLEX ras error records
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* ERRSELR: 4*256 + Unit_ID, Unit_ID: 0 - 4
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* 1 groups, 5 nodes in total.
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*/
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ADD_ONE_ERR_GROUP(0x400, ccplex_ras_group),
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};
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REGISTER_ERR_RECORD_INFO(carmel_ras_records);
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/* dummy RAS interrupt */
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static struct ras_interrupt carmel_ras_interrupts[] = {};
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REGISTER_RAS_INTERRUPTS(carmel_ras_interrupts);
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/*******************************************************************************
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* RAS handler for the platform
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******************************************************************************/
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void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
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void *handle, uint64_t flags)
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{
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#if RAS_EXTENSION
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tegra194_ea_handler(ea_reason, syndrome, cookie, handle, flags);
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#else
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ERROR("Unhandled External Abort received on 0x%llx at EL3!\n",
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read_mpidr_el1());
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ERROR(" exception reason=%u syndrome=0x%lx\n", ea_reason, syndrome);
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panic();
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#endif
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}
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