157 lines
5.2 KiB
C
157 lines
5.2 KiB
C
/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VERSAL_DEF_H
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#define VERSAL_DEF_H
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#include <plat/arm/common/smccc_def.h>
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#include <plat/common/common_def.h>
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/* List all consoles */
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#define VERSAL_CONSOLE_ID_pl011 1
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#define VERSAL_CONSOLE_ID_pl011_0 1
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#define VERSAL_CONSOLE_ID_pl011_1 2
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#define VERSAL_CONSOLE_ID_dcc 3
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#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
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/* List all supported platforms */
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#define VERSAL_PLATFORM_ID_versal_virt 1
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#define VERSAL_PLATFORM_ID_spp_itr6 2
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#define VERSAL_PLATFORM_ID_emu_itr6 3
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#define VERSAL_PLATFORM_ID_silicon 4
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#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
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/* Firmware Image Package */
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#define VERSAL_PRIMARY_CPU 0
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/*******************************************************************************
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* memory map related constants
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******************************************************************************/
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#define DEVICE0_BASE 0xFF000000
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#define DEVICE0_SIZE 0x00E00000
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#define DEVICE1_BASE 0xF9000000
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#define DEVICE1_SIZE 0x00800000
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/* CRL */
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#define VERSAL_CRL 0xFF5E0000
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#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C)
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#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348)
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#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25)
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/* IOU SCNTRS */
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#define VERSAL_IOU_SCNTRS 0xFF140000
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#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0)
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#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20)
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#define VERSAL_IOU_SCNTRS_CONTROL_EN 1
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/*******************************************************************************
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* IRQ constants
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******************************************************************************/
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#define VERSAL_IRQ_SEC_PHY_TIMER U(29)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_ARM_CCI_BASE 0xFD000000
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define VERSAL_UART0_BASE 0xFF000000
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#define VERSAL_UART1_BASE 0xFF010000
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#if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
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# define VERSAL_UART_BASE VERSAL_UART0_BASE
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#elif VERSAL_CONSOLE_IS(pl011_1)
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# define VERSAL_UART_BASE VERSAL_UART1_BASE
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#else
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# error "invalid VERSAL_CONSOLE"
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#endif
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#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
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#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
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#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
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/*******************************************************************************
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* Platform related constants
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******************************************************************************/
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#if VERSAL_PLATFORM_IS(versal_virt)
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# define PLATFORM_NAME "Versal Virt"
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# define VERSAL_UART_CLOCK 25000000
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# define VERSAL_UART_BAUDRATE 115200
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# define VERSAL_CPU_CLOCK 2720000
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#elif VERSAL_PLATFORM_IS(silicon)
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# define PLATFORM_NAME "Versal Silicon"
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# define VERSAL_UART_CLOCK 100000000
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# define VERSAL_UART_BAUDRATE 115200
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# define VERSAL_CPU_CLOCK 100000000
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#elif VERSAL_PLATFORM_IS(spp_itr6)
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# define PLATFORM_NAME "SPP ITR6"
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# define VERSAL_UART_CLOCK 25000000
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# define VERSAL_UART_BAUDRATE 115200
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# define VERSAL_CPU_CLOCK 2720000
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#elif VERSAL_PLATFORM_IS(emu_itr6)
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# define PLATFORM_NAME "EMU ITR6"
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# define VERSAL_UART_CLOCK 212000
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# define VERSAL_UART_BAUDRATE 9600
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# define VERSAL_CPU_CLOCK 212000
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#endif
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/* Access control register defines */
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
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#define CRF_BASE 0xFD1A0000
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#define CRF_SIZE 0x00600000
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/* CRF registers and bitfields */
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#define CRF_RST_APU (CRF_BASE + 0X00000300)
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#define CRF_RST_APU_ACPU_RESET (1 << 0)
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#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
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#define FPD_MAINCCI_BASE 0xFD000000
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#define FPD_MAINCCI_SIZE 0x00100000
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/* APU registers and bitfields */
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#define FPD_APU_BASE 0xFD5C0000U
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#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
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#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U)
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#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U)
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#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U)
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#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U
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#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U
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#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U
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/* PMC registers and bitfields */
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#define PMC_GLOBAL_BASE 0xF1110000U
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#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
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/* IPI registers and bitfields */
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#define IPI0_REG_BASE U(0xFF330000)
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#define IPI0_TRIG_BIT (1U << 2U)
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#define PMC_IPI_TRIG_BIT (1U << 1U)
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#define IPI1_REG_BASE U(0xFF340000)
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#define IPI1_TRIG_BIT (1U << 3U)
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#define IPI2_REG_BASE U(0xFF350000)
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#define IPI2_TRIG_BIT (1U << 4U)
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#define IPI3_REG_BASE U(0xFF360000)
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#define IPI3_TRIG_BIT (1U << 5U)
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#define IPI4_REG_BASE U(0xFF370000)
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#define IPI4_TRIG_BIT (1U << 5U)
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#define IPI5_REG_BASE U(0xFF380000)
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#define IPI5_TRIG_BIT (1U << 6U)
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#endif /* VERSAL_DEF_H */
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