Louis Mayencourt 0e985d708e DSU: Implement workaround for errata 798953 ... Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2019-04-17 13:46:43 +01:00
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aarch32	Cortex A9:errata 794073 workaround	2019-04-12 10:10:32 +00:00
aarch64	DSU: Implement workaround for errata 798953	2019-04-17 13:46:43 +01:00
cpu-ops.mk	DSU: Implement workaround for errata 798953	2019-04-17 13:46:43 +01:00
errata_report.c	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00