Arunachalam Ganapathy 68ac5ed049 fix(el3_runtime): fix SVE and AMU extension enablement flags ... If SVE are enabled for both Non-secure and Secure world along with AMU extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit from bl31. This restricts access to the AMU register set in normal world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT by saving and restoring CPTR_EL3 register from EL3 context. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087		2021-07-23 10:33:59 +01:00
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amu.h	fix(el3_runtime): fix SVE and AMU extension enablement flags	2021-07-23 10:33:59 +01:00
amu_private.h	Enable v8.6 AMU enhancements (FEAT_AMUv1p1)	2021-02-25 22:01:59 +00:00
mpam.h	refactor(mpam): remove unused function declaration	2021-07-09 22:03:38 +02:00
pauth.h	Refactor ARMv8.3 Pointer Authentication support code	2019-09-13 14:11:59 +01:00
ras.h	Tegra194: add RAS exception handling	2020-06-12 09:43:54 -07:00
ras_arch.h	Tegra194: add RAS exception handling	2020-06-12 09:43:54 -07:00
spe.h	Fix MISRA defects in extension libs	2018-10-29 14:41:48 +00:00
sve.h	feat(sve): enable SVE for the secure world	2021-06-28 13:24:24 +01:00
twed.h	Enable v8.6 WFE trap delays	2020-05-19 21:49:52 +00:00