Dimitris Papastamos 1d6d47a82a Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75 ... This patch implements a fast path for this SMC call on affected PEs by detecting and returning immediately after executing the workaround. NOTE: The MMU disable/enable workaround now assumes that the MMU was enabled on entry to EL3. This is a valid assumption as the code turns on the MMU after reset and leaves it on until the core powers off. Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>		2018-01-29 09:58:57 +00:00
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aarch32	Merge pull request #1228 from dp-arm/dp/cve_2017_5715	2018-01-25 00:06:50 +00:00
aarch64	Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75	2018-01-29 09:58:57 +00:00
cpu-ops.mk	Workaround for CVE-2017-5715 on Cortex A57 and A72	2018-01-11 10:26:15 +00:00
errata_report.c	Merge pull request #1228 from dp-arm/dp/cve_2017_5715	2018-01-25 00:06:50 +00:00