214 lines
6.3 KiB
ArmAsm
214 lines
6.3 KiB
ArmAsm
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <gicv2.h>
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#include <gicv3.h>
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#include <platform_def.h>
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#include <v2m_def.h>
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#include "../drivers/pwrc/fvp_pwrc.h"
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#include "../fvp_def.h"
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.globl plat_secondary_cold_boot_setup
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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.globl plat_arm_calc_core_pos
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.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
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ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID
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ldr \w_tmp, [\x_tmp]
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ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
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cmp \w_tmp, #BLD_GIC_VE_MMAP
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csel \res, \param1, \param2, eq
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.endm
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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#ifndef EL3_PAYLOAD_BASE
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/* ---------------------------------------------
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* Power down this cpu.
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* TODO: Do we need to worry about powering the
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* cluster down as well here. That will need
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* locks which we won't have unless an elf-
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* loader zeroes out the zi section.
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* ---------------------------------------------
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*/
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mrs x0, mpidr_el1
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ldr x1, =PWRC_BASE
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str w0, [x1, #PPOFFR_OFF]
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/* ---------------------------------------------
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* Disable GIC bypass as well
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* ---------------------------------------------
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*/
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/* Check for GICv3 system register access */
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x0, #1
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b.ne gicv2_bypass_disable
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/* Check for SRE enable */
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mrs x1, ICC_SRE_EL3
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tst x1, #ICC_SRE_SRE_BIT
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b.eq gicv2_bypass_disable
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mrs x2, ICC_SRE_EL3
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orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
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msr ICC_SRE_EL3, x2
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b secondary_cold_boot_wait
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gicv2_bypass_disable:
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ldr x0, =VE_GICC_BASE
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ldr x1, =BASE_GICC_BASE
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fvp_choose_gicmmap x0, x1, x2, w2, x1
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mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
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orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
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str w0, [x1, #GICC_CTLR]
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secondary_cold_boot_wait:
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/* ---------------------------------------------
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* There is no sane reason to come out of this
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* wfi so panic if we do. This cpu will be pow-
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* ered on and reset by the cpu_on pm api
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* ---------------------------------------------
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*/
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dsb sy
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wfi
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no_ret plat_panic_handler
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#else
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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/* Wait until the entrypoint gets populated */
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poll_mailbox:
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ldr x1, [x0]
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cbz x1, 1f
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br x1
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1:
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wfe
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b poll_mailbox
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#endif /* EL3_PAYLOAD_BASE */
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and warm
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* boot. On FVP, this information can be queried from the power
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* controller. The Power Control SYS Status Register (PSYSR) indicates
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* the wake-up reason for the CPU.
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*
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* For a cold boot, return 0.
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* For a warm boot, read the mailbox and return the address it contains.
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*
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* TODO: PSYSR is a common register and should be
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* accessed using locks. Since it is not possible
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* to use locks immediately after a cold reset
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* we are relying on the fact that after a cold
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* reset all cpus will read the same WK field
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* ---------------------------------------------------------------------
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* When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC
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* WakeRequest signal" then it is a warm boot.
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* ---------------------------------------------------------------------
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*/
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mrs x2, mpidr_el1
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ldr x1, =PWRC_BASE
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str w2, [x1, #PSYSR_OFF]
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ldr w2, [x1, #PSYSR_OFF]
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ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
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cmp w2, #WKUP_PPONR
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beq warm_reset
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cmp w2, #WKUP_GICREQ
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beq warm_reset
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/* Cold reset */
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mov x0, #0
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ret
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warm_reset:
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/* ---------------------------------------------------------------------
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* A mailbox is maintained in the trusted SRAM. It is flushed out of the
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* caches after every update using normal memory so it is safe to read
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* it here with SO attributes.
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* ---------------------------------------------------------------------
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*/
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr x0, [x0]
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cbz x0, _panic_handler
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ret
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/* ---------------------------------------------------------------------
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* The power controller indicates this is a warm reset but the mailbox
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* is empty. This should never happen!
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* ---------------------------------------------------------------------
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*/
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_panic_handler:
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no_ret plat_panic_handler
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endfunc plat_get_my_entrypoint
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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ldr x1, =MPIDR_AFFINITY_MASK
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and x0, x0, x1
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cmp x0, #FVP_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Function to calculate the core position on FVP.
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*
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* (ClusterId * FVP_MAX_CPUS_PER_CLUSTER) +
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* (CPUId * FVP_MAX_PE_PER_CPU) +
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* ThreadId
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* -----------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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mov x3, x0
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/*
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* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
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* look as if in a multi-threaded implementation.
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*/
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tst x0, #MPIDR_MT_MASK
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lsl x3, x0, #MPIDR_AFFINITY_BITS
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csel x3, x3, x0, eq
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/* Extract individual affinity fields from MPIDR */
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ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov x4, #FVP_MAX_PE_PER_CPU
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madd x0, x1, x4, x0
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mov x5, #FVP_MAX_CPUS_PER_CLUSTER
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madd x0, x2, x5, x0
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ret
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endfunc plat_arm_calc_core_pos
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