220 lines
7.3 KiB
C
220 lines
7.3 KiB
C
/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <bl31.h>
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#include <debug.h>
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#include <context_mgmt.h>
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#include <platform.h>
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#include <runtime_svc.h>
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#include <stddef.h>
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#include "psci_private.h"
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/*******************************************************************************
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* This function checks whether a cpu which has been requested to be turned on
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* is OFF to begin with.
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******************************************************************************/
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static int cpu_on_validate_state(unsigned int psci_state)
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{
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if (psci_state == PSCI_STATE_ON || psci_state == PSCI_STATE_SUSPEND)
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return PSCI_E_ALREADY_ON;
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if (psci_state == PSCI_STATE_ON_PENDING)
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return PSCI_E_ON_PENDING;
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assert(psci_state == PSCI_STATE_OFF);
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Generic handler which is called to physically power on a cpu identified by
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* its mpidr. It performs the generic, architectural, platform setup and state
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* management to power on the target cpu e.g. it will ensure that
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* enough information is stashed for it to resume execution in the non-secure
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* security state.
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*
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* The state of all the relevant power domains are changed after calling the
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* platform handler as it can return error.
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******************************************************************************/
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int psci_cpu_on_start(unsigned long target_cpu,
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entry_point_info_t *ep,
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int end_pwrlvl)
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{
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int rc;
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mpidr_pwr_map_nodes_t target_cpu_nodes;
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unsigned long psci_entrypoint;
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/*
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* This function must only be called on platforms where the
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* CPU_ON platform hooks have been implemented.
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*/
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assert(psci_plat_pm_ops->pwr_domain_on &&
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psci_plat_pm_ops->pwr_domain_on_finish);
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/*
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* Collect the pointers to the nodes in the topology tree for
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* each power domain instance in the mpidr. If this function does
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* not return successfully then either the mpidr or the power
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* levels are incorrect.
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*/
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rc = psci_get_pwr_map_nodes(target_cpu,
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MPIDR_AFFLVL0,
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end_pwrlvl,
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target_cpu_nodes);
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assert(rc == PSCI_E_SUCCESS);
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/*
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* This function acquires the lock corresponding to each power
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* level so that by the time all locks are taken, the system topology
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* is snapshot and state management can be done safely.
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*/
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psci_acquire_pwr_domain_locks(MPIDR_AFFLVL0,
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end_pwrlvl,
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target_cpu_nodes);
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/*
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* Generic management: Ensure that the cpu is off to be
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* turned on.
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*/
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rc = cpu_on_validate_state(psci_get_state(
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target_cpu_nodes[MPIDR_AFFLVL0]));
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if (rc != PSCI_E_SUCCESS)
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goto exit;
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/*
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* Call the cpu on handler registered by the Secure Payload Dispatcher
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* to let it do any bookeeping. If the handler encounters an error, it's
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* expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_on)
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psci_spd_pm->svc_on(target_cpu);
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/*
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* This function updates the state of each affinity instance
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* corresponding to the mpidr in the range of affinity levels
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* specified.
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*/
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psci_do_state_coordination(MPIDR_AFFLVL0,
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end_pwrlvl,
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target_cpu_nodes,
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PSCI_STATE_ON_PENDING);
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/*
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* Perform generic, architecture and platform specific handling.
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*/
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/* Set the secure world (EL3) re-entry point after BL1 */
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psci_entrypoint = (unsigned long) psci_cpu_on_finish_entry;
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/*
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* Plat. management: Give the platform the current state
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* of the target cpu to allow it to perform the necessary
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* steps to power on.
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*/
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rc = psci_plat_pm_ops->pwr_domain_on(target_cpu,
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psci_entrypoint,
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MPIDR_AFFLVL0);
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assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
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if (rc == PSCI_E_SUCCESS)
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/* Store the re-entry information for the non-secure world. */
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cm_init_context_by_index(target_idx, ep);
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else
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/* Restore the state on error. */
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psci_do_state_coordination(MPIDR_AFFLVL0,
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end_pwrlvl,
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target_cpu_nodes,
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PSCI_STATE_OFF);
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exit:
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/*
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* This loop releases the lock corresponding to each power level
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* in the reverse order to which they were acquired.
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*/
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psci_release_pwr_domain_locks(MPIDR_AFFLVL0,
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end_pwrlvl,
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target_cpu_nodes);
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return rc;
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}
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/*******************************************************************************
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* The following function finish an earlier power on request. They
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* are called by the common finisher routine in psci_common.c.
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******************************************************************************/
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void psci_cpu_on_finish(pwr_map_node_t *node[], int pwrlvl)
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{
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assert(node[pwrlvl]->level == pwrlvl);
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/* Ensure we have been explicitly woken up by another cpu */
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assert(psci_get_state(node[MPIDR_AFFLVL0]) == PSCI_STATE_ON_PENDING);
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/*
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* Plat. management: Perform the platform specific actions
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* for this cpu e.g. enabling the gic or zeroing the mailbox
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* register. The actual state of this cpu has already been
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* changed.
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*/
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psci_plat_pm_ops->pwr_domain_on_finish(pwrlvl);
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/*
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* Arch. management: Enable data cache and manage stack memory
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*/
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psci_do_pwrup_cache_maintenance();
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/*
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* All the platform specific actions for turning this cpu
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* on have completed. Perform enough arch.initialization
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* to run in the non-secure address space.
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*/
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bl31_arch_setup();
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/*
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* Call the cpu on finish handler registered by the Secure Payload
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* Dispatcher to let it do any bookeeping. If the handler encounters an
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* error, it's expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_on_finish)
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psci_spd_pm->svc_on_finish(0);
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/*
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* Generic management: Now we just need to retrieve the
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* information that we had stashed away during the cpu_on
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* call to set this cpu on its way.
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*/
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cm_prepare_el3_exit(NON_SECURE);
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/* Clean caches before re-entering normal world */
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dcsw_op_louis(DCCSW);
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}
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