34 lines
1022 B
C
34 lines
1022 B
C
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MORELLO_DEF_H
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#define MORELLO_DEF_H
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/* Non-secure SRAM MMU mapping */
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#define MORELLO_NS_SRAM_BASE UL(0x06000000)
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#define MORELLO_NS_SRAM_SIZE UL(0x00010000)
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#define MORELLO_MAP_NS_SRAM MAP_REGION_FLAT( \
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MORELLO_NS_SRAM_BASE, \
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MORELLO_NS_SRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* SDS Platform information defines */
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#define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8)
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#define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0)
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#define MORELLO_SDS_PLATFORM_INFO_SIZE U(4)
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#define MORELLO_MAX_DDR_CAPACITY_GB U(64)
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#define MORELLO_MAX_SLAVE_COUNT U(16)
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/* SDS BL33 image information defines */
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#define MORELLO_SDS_BL33_INFO_STRUCT_ID U(9)
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#define MORELLO_SDS_BL33_INFO_OFFSET U(0)
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#define MORELLO_SDS_BL33_INFO_SIZE U(12)
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/* Base address of non-secure SRAM where Platform information will be filled */
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#define MORELLO_PLATFORM_INFO_BASE UL(0x06008000)
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#endif /* MORELLO_DEF_H */
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