74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <bl_common.h>
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#include <gicv3.h>
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#include <plat_imx8.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <utils.h>
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/* the GICv3 driver only needs to be initialized in EL3 */
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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/* array of Group1 secure interrupts to be configured by the gic driver */
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const unsigned int g1s_interrupt_array[] = { 6 };
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/* array of Group0 interrupts to be configured by the gic driver */
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const unsigned int g0_interrupt_array[] = { 7 };
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static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)
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{
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return (unsigned int)plat_core_pos_by_mpidr(mpidr);
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}
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const gicv3_driver_data_t arm_gic_data = {
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.gicd_base = PLAT_GICD_BASE,
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.gicr_base = PLAT_GICR_BASE,
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.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
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.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
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.g0_interrupt_array = g0_interrupt_array,
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.g1s_interrupt_array = g1s_interrupt_array,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = plat_imx_mpidr_to_core_pos,
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};
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void plat_gic_driver_init(void)
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{
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/*
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* the GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in S-EL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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#if IMAGE_BL31
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gicv3_driver_init(&arm_gic_data);
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#endif
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}
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void plat_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void plat_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void plat_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void plat_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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