Anson Huang 1552df5d25 Support for NXP's i.MX8 SoCs timer IPC ... NXP's i.MX8 SoCs have system controller (M4 core) which takes control of timer management, including watchdog, srtc and system counter etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for timer operation. This patch adds timer IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>		2019-01-17 10:49:48 +08:00
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allwinner	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
arm	Merge pull request #1738 from ardbiesheuvel/synquacer-spm	2019-01-16 16:01:42 +00:00
common	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
hisilicon	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
imx	Support for NXP's i.MX8 SoCs timer IPC	2019-01-17 10:49:48 +08:00
layerscape	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
marvell	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
mediatek	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
meson/gxbb	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
nvidia/tegra	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
qemu	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
renesas/rcar	rcar_gen3: plat: update renesas version to 2.0.0	2019-01-08 14:08:44 +01:00
rockchip	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
rpi3	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
socionext	plat/synquacer: enable SPM support	2019-01-15 17:51:23 +01:00
st/stm32mp1	stm32mp1: do not include platform header files directly in drivers	2019-01-07 11:17:24 +01:00
ti/k3	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
xilinx	xilinx: Move IPI functions to common file	2019-01-09 12:38:00 -08:00