128 lines
5.4 KiB
C
128 lines
5.4 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __TEGRA_DEF_H__
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#define __TEGRA_DEF_H__
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#include <utils_def.h>
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/*******************************************************************************
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* Power down state IDs
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******************************************************************************/
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#define PSTATE_ID_CORE_POWERDN U(7)
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#define PSTATE_ID_CLUSTER_IDLE U(16)
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#define PSTATE_ID_CLUSTER_POWERDN U(17)
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#define PSTATE_ID_SOC_POWERDN U(27)
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/*******************************************************************************
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* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call as the `state-id` field in the 'power state' parameter.
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******************************************************************************/
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#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN
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/*******************************************************************************
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* Platform power states (used by PSCI framework)
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*
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* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
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* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
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******************************************************************************/
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
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/*******************************************************************************
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* GIC memory map
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******************************************************************************/
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#define TEGRA_GICD_BASE U(0x50041000)
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#define TEGRA_GICC_BASE U(0x50042000)
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/*******************************************************************************
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* Tegra Memory Select Switch Controller constants
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******************************************************************************/
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#define TEGRA_MSELECT_BASE U(0x50060000)
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#define MSELECT_CONFIG U(0x0)
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#define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29))
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#define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28))
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#define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27))
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#define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25))
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#define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24))
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#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \
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UNSUPPORTED_TX_ERR_MASTER1_BIT)
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#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \
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ENABLE_WRAP_INCR_MASTER1_BIT | \
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ENABLE_WRAP_INCR_MASTER0_BIT)
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE U(0x60005010)
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#define TEGRA_TMRUS_SIZE U(0x1000)
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE U(0x60006000)
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#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
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#define GPU_RESET_BIT (U(1) << 24)
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/*******************************************************************************
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* Tegra Flow Controller constants
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******************************************************************************/
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#define TEGRA_FLOWCTRL_BASE U(0x60007000)
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/*******************************************************************************
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* Tegra Secure Boot Controller constants
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******************************************************************************/
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#define TEGRA_SB_BASE U(0x6000C200)
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/*******************************************************************************
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* Tegra Exception Vectors constants
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******************************************************************************/
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#define TEGRA_EVP_BASE U(0x6000F000)
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/*******************************************************************************
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* Tegra Miscellaneous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE U(0x70000000)
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#define HARDWARE_REVISION_OFFSET U(0x804)
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/*******************************************************************************
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* Tegra UART controller base addresses
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******************************************************************************/
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#define TEGRA_UARTA_BASE U(0x70006000)
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#define TEGRA_UARTB_BASE U(0x70006040)
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#define TEGRA_UARTC_BASE U(0x70006200)
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#define TEGRA_UARTD_BASE U(0x70006300)
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#define TEGRA_UARTE_BASE U(0x70006400)
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE U(0x7000E400)
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_BASE U(0x70019000)
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 U(0x70)
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#define MC_SECURITY_CFG1_0 U(0x74)
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#define MC_SECURITY_CFG3_0 U(0x9BC)
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
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#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
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#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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#define TEGRA_TZRAM_BASE U(0x7C010000)
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#define TEGRA_TZRAM_SIZE U(0x10000)
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#endif /* __TEGRA_DEF_H__ */
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