138 lines
3.0 KiB
ArmAsm
138 lines
3.0 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <pmu_regs.h>
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.globl clst_warmboot_data
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.macro sram_func _name
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.cfi_sections .debug_frame
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.section .sram.text, "ax"
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.type \_name, %function
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.func \_name
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.cfi_startproc
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\_name:
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.endm
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#define CRU_CLKSEL_CON6 0x118
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#define DDRCTL0_C_SYSREQ_CFG 0x0100
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#define DDRCTL1_C_SYSREQ_CFG 0x1000
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#define DDRC0_SREF_DONE_EXT 0x01
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#define DDRC1_SREF_DONE_EXT 0x04
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#define PLL_MODE_SHIFT (0x8)
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#define PLL_NORMAL_MODE ((0x3 << (PLL_MODE_SHIFT + 16)) | \
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(0x1 << PLL_MODE_SHIFT))
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#define MPIDR_CLST_L_BITS 0x0
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/*
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* For different socs, if we want to speed up warmboot,
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* we need to config some regs here.
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* If scu was suspend, we must resume related clk
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* from slow (24M) mode to normal mode first.
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* X0: MPIDR_EL1 & MPIDR_CLUSTER_MASK
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*/
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.macro func_rockchip_clst_warmboot
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adr x4, clst_warmboot_data
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lsr x5, x0, #6
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ldr w3, [x4, x5]
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str wzr, [x4, x5]
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cmp w3, #PMU_CLST_RET
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b.ne clst_warmboot_end
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ldr w6, =(PLL_NORMAL_MODE)
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/*
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* core_l offset is CRU_BASE + 0xc,
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* core_b offset is CRU_BASE + 0x2c
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*/
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ldr x7, =(CRU_BASE + 0xc)
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lsr x2, x0, #3
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str w6, [x7, x2]
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clst_warmboot_end:
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.endm
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.macro rockchip_clst_warmboot_data
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clst_warmboot_data:
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.rept PLATFORM_CLUSTER_COUNT
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.word 0
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.endr
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.endm
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/* -----------------------------------------------
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* void sram_func_set_ddrctl_pll(uint32_t pll_src)
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* Function to switch the PLL source for ddrctrl
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* In: x0 - The PLL of the clk_ddrc clock source
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* out: None
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* Clobber list : x0 - x3, x5, x8 - x10
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* -----------------------------------------------
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*/
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.globl sram_func_set_ddrctl_pll
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sram_func sram_func_set_ddrctl_pll
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/* backup parameter */
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mov x8, x0
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/* disable the MMU at EL3 */
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mrs x9, sctlr_el3
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bic x10, x9, #(SCTLR_M_BIT)
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msr sctlr_el3, x10
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isb
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dsb sy
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/* enable ddrctl0_1 idle request */
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mov x5, PMU_BASE
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ldr w0, [x5, #PMU_SFT_CON]
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orr w0, w0, #DDRCTL0_C_SYSREQ_CFG
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orr w0, w0, #DDRCTL1_C_SYSREQ_CFG
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str w0, [x5, #PMU_SFT_CON]
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check_ddrc0_1_sref_enter:
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ldr w1, [x5, #PMU_DDR_SREF_ST]
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and w2, w1, #DDRC0_SREF_DONE_EXT
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and w3, w1, #DDRC1_SREF_DONE_EXT
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orr w2, w2, w3
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cmp w2, #(DDRC0_SREF_DONE_EXT | DDRC1_SREF_DONE_EXT)
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b.eq check_ddrc0_1_sref_enter
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/*
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* select a PLL for ddrctrl:
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* x0 = 0: ALPLL
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* x0 = 1: ABPLL
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* x0 = 2: DPLL
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* x0 = 3: GPLLL
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*/
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mov x5, CRU_BASE
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lsl w0, w8, #4
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orr w0, w0, #0x00300000
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str w0, [x5, #CRU_CLKSEL_CON6]
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/* disable ddrctl0_1 idle request */
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mov x5, PMU_BASE
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ldr w0, [x5, #PMU_SFT_CON]
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bic w0, w0, #DDRCTL0_C_SYSREQ_CFG
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bic w0, w0, #DDRCTL1_C_SYSREQ_CFG
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str w0, [x5, #PMU_SFT_CON]
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check_ddrc0_1_sref_exit:
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ldr w1, [x5, #PMU_DDR_SREF_ST]
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and w2, w1, #DDRC0_SREF_DONE_EXT
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and w3, w1, #DDRC1_SREF_DONE_EXT
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orr w2, w2, w3
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cmp w2, #0x0
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b.eq check_ddrc0_1_sref_exit
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/* reenable the MMU at EL3 */
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msr sctlr_el3, x9
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isb
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dsb sy
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ret
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endfunc sram_func_set_ddrctl_pll
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