310 lines
10 KiB
C
310 lines
10 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <debug.h>
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#include <platform.h>
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#include <platform_def.h>
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#include "psci_private.h"
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#ifndef PLAT_MAX_PWR_LVL_STATES
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#define PLAT_MAX_PWR_LVL_STATES 2
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#endif
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/* Ticks elapsed in one second by a signal of 1 MHz */
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#define MHZ_TICKS_PER_SEC 1000000
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/* Following structure is used for PSCI STAT */
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typedef struct psci_stat {
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u_register_t residency;
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u_register_t count;
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} psci_stat_t;
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/*
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* Following is used to keep track of the last cpu
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* that goes to power down in non cpu power domains.
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*/
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static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1};
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/*
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* Following are used to store PSCI STAT values for
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* CPU and non CPU power domains.
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*/
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static psci_stat_t psci_cpu_stat[PLATFORM_CORE_COUNT]
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[PLAT_MAX_PWR_LVL_STATES];
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static psci_stat_t psci_non_cpu_stat[PSCI_NUM_NON_CPU_PWR_DOMAINS]
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[PLAT_MAX_PWR_LVL_STATES];
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/* Register PMF PSCI service */
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PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID,
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PSCI_STAT_TOTAL_IDS, PMF_STORE_ENABLE)
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/* The divisor to use to convert raw timestamp into microseconds */
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u_register_t residency_div;
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/*
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* This macro calculates the stats residency in microseconds,
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* taking in account the wrap around condition.
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*/
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#define calc_stat_residency(_pwrupts, _pwrdnts, _res) \
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do { \
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if (_pwrupts < _pwrdnts) \
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_res = UINT64_MAX - _pwrdnts + _pwrupts;\
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else \
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_res = _pwrupts - _pwrdnts; \
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/* Convert timestamp into microseconds */ \
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_res = _res/residency_div; \
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} while (0)
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/*
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* This functions returns the index into the `psci_stat_t` array given the
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* local power state and power domain level. If the platform implements the
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* `get_pwr_lvl_state_idx` pm hook, then that will be used to return the index.
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*/
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static int get_stat_idx(plat_local_state_t local_state, int pwr_lvl)
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{
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int idx;
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if (psci_plat_pm_ops->get_pwr_lvl_state_idx == NULL) {
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assert(PLAT_MAX_PWR_LVL_STATES == 2);
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if (is_local_state_retn(local_state))
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return 0;
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assert(is_local_state_off(local_state));
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return 1;
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}
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idx = psci_plat_pm_ops->get_pwr_lvl_state_idx(local_state, pwr_lvl);
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assert((idx >= 0) && (idx < PLAT_MAX_PWR_LVL_STATES));
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return idx;
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}
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/*******************************************************************************
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* This function is passed the target local power states for each power
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* domain (state_info) between the current CPU domain and its ancestors until
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* the target power level (end_pwrlvl).
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*
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* Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it
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* updates the `last_cpu_in_non_cpu_pd[]` with last power down cpu id.
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*
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* This function will only be invoked with data cache enabled and while
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* powering down a core.
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******************************************************************************/
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void psci_stats_update_pwr_down(unsigned int end_pwrlvl,
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const psci_power_state_t *state_info)
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{
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int lvl, parent_idx, cpu_idx = plat_my_core_pos();
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assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
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assert(state_info);
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parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
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for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
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/* Break early if the target power state is RUN */
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if (is_local_state_run(state_info->pwr_domain_state[lvl]))
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break;
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/*
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* The power domain is entering a low power state, so this is
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* the last CPU for this power domain
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*/
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last_cpu_in_non_cpu_pd[parent_idx] = cpu_idx;
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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}
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/*******************************************************************************
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* This function updates the PSCI STATS(residency time and count) for CPU
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* and NON-CPU power domains.
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* It is called with caches enabled and locks acquired(for NON-CPU domain)
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******************************************************************************/
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void psci_stats_update_pwr_up(unsigned int end_pwrlvl,
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const psci_power_state_t *state_info,
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unsigned int flags)
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{
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int parent_idx, cpu_idx = plat_my_core_pos();
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int lvl, stat_idx;
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plat_local_state_t local_state;
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unsigned long long pwrup_ts = 0, pwrdn_ts = 0;
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u_register_t residency;
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assert(end_pwrlvl <= PLAT_MAX_PWR_LVL);
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assert(state_info);
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/* Initialize the residency divisor if not already initialized */
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if (!residency_div) {
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/* Pre-calculate divisor so that it can be directly used to
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convert time-stamp into microseconds */
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residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC;
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assert(residency_div);
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}
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/* Get power down time-stamp for current CPU */
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PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
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cpu_idx, flags, pwrdn_ts);
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/* In the case of 1st power on just return */
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if (!pwrdn_ts)
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return;
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/* Get power up time-stamp for current CPU */
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PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
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cpu_idx, flags, pwrup_ts);
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/* Get the index into the stats array */
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local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL];
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stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL);
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/* Calculate stats residency */
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calc_stat_residency(pwrup_ts, pwrdn_ts, residency);
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/* Update CPU stats. */
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psci_cpu_stat[cpu_idx][stat_idx].residency += residency;
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psci_cpu_stat[cpu_idx][stat_idx].count++;
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/*
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* Check what power domains above CPU were off
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* prior to this CPU powering on.
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*/
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parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node;
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for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) {
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local_state = state_info->pwr_domain_state[lvl];
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if (is_local_state_run(local_state)) {
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/* Break early */
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break;
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}
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assert(last_cpu_in_non_cpu_pd[parent_idx] != -1);
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/* Get power down time-stamp for last CPU */
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PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
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last_cpu_in_non_cpu_pd[parent_idx],
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flags, pwrdn_ts);
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/* Initialize back to reset value */
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last_cpu_in_non_cpu_pd[parent_idx] = -1;
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/* Get the index into the stats array */
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stat_idx = get_stat_idx(local_state, lvl);
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/* Calculate stats residency */
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calc_stat_residency(pwrup_ts, pwrdn_ts, residency);
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/* Update non cpu stats */
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psci_non_cpu_stat[parent_idx][stat_idx].residency += residency;
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psci_non_cpu_stat[parent_idx][stat_idx].count++;
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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}
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}
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/*******************************************************************************
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* This function returns the appropriate count and residency time of the
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* local state for the highest power level expressed in the `power_state`
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* for the node represented by `target_cpu`.
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******************************************************************************/
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int psci_get_stat(u_register_t target_cpu, unsigned int power_state,
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psci_stat_t *psci_stat)
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{
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int rc, pwrlvl, lvl, parent_idx, stat_idx, target_idx;
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psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
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plat_local_state_t local_state;
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/* Validate the target_cpu parameter and determine the cpu index */
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target_idx = plat_core_pos_by_mpidr(target_cpu);
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if (target_idx == -1)
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return PSCI_E_INVALID_PARAMS;
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/* Validate the power_state parameter */
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if (!psci_plat_pm_ops->translate_power_state_by_mpidr)
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rc = psci_validate_power_state(power_state, &state_info);
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else
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rc = psci_plat_pm_ops->translate_power_state_by_mpidr(
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target_cpu, power_state, &state_info);
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if (rc != PSCI_E_SUCCESS)
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return PSCI_E_INVALID_PARAMS;
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/* Find the highest power level */
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pwrlvl = psci_find_target_suspend_lvl(&state_info);
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if (pwrlvl == PSCI_INVALID_PWR_LVL)
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return PSCI_E_INVALID_PARAMS;
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/* Get the index into the stats array */
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local_state = state_info.pwr_domain_state[pwrlvl];
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stat_idx = get_stat_idx(local_state, pwrlvl);
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if (pwrlvl > PSCI_CPU_PWR_LVL) {
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/* Get the power domain index */
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parent_idx = psci_cpu_pd_nodes[target_idx].parent_node;
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for (lvl = PSCI_CPU_PWR_LVL + 1; lvl < pwrlvl; lvl++)
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parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node;
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/* Get the non cpu power domain stats */
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*psci_stat = psci_non_cpu_stat[parent_idx][stat_idx];
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} else {
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/* Get the cpu power domain stats */
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*psci_stat = psci_cpu_stat[target_idx][stat_idx];
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}
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return PSCI_E_SUCCESS;
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}
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/* This is the top level function for PSCI_STAT_RESIDENCY SMC. */
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u_register_t psci_stat_residency(u_register_t target_cpu,
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unsigned int power_state)
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{
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psci_stat_t psci_stat;
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int rc = psci_get_stat(target_cpu, power_state, &psci_stat);
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if (rc == PSCI_E_SUCCESS)
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return psci_stat.residency;
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else
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return 0;
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}
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/* This is the top level function for PSCI_STAT_COUNT SMC. */
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u_register_t psci_stat_count(u_register_t target_cpu,
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unsigned int power_state)
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{
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psci_stat_t psci_stat;
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int rc = psci_get_stat(target_cpu, power_state, &psci_stat);
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if (rc == PSCI_E_SUCCESS)
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return psci_stat.count;
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else
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return 0;
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}
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