304 lines
8.7 KiB
C
304 lines
8.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <debug.h>
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#include <desc_image_load.h>
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#include <mmc.h>
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#include <mmio.h>
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#include <optee_utils.h>
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#include <platform_def.h>
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#include <utils.h>
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#include <xlat_mmu_helpers.h>
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#include <xlat_tables_defs.h>
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#include <imx_aips.h>
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#include <imx_caam.h>
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#include <imx_clock.h>
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#include <imx_csu.h>
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#include <imx_gpt.h>
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#include <imx_io_mux.h>
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#include <imx_uart.h>
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#include <imx_snvs.h>
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#include <imx_usdhc.h>
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#include <imx_wdog.h>
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#include "warp7_private.h"
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#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
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#define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M)
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#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
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CCM_TARGET_POST_PODF(2))
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#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
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#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
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CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return WARP7_UBOOT_BASE;
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}
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static uint32_t warp7_get_spsr_for_bl32_entry(void)
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{
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return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
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DISABLE_ALL_EXCEPTIONS);
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}
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static uint32_t warp7_get_spsr_for_bl33_entry(void)
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{
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return SPSR_MODE32(MODE32_svc,
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plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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}
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#ifndef AARCH32_SP_OPTEE
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#error "Must build with OPTEE support included"
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#endif
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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bl_mem_params_node_t *hw_cfg_mem_params = NULL;
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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assert(bl_mem_params);
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switch (image_id) {
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case BL32_IMAGE_ID:
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0)
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WARN("OPTEE header parse error.\n");
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/*
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* When ATF loads the DTB the address of the DTB is passed in
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* arg2, if an hw config image is present use the base address
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* as DTB address an pass it as arg2
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*/
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hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
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bl_mem_params->ep_info.args.arg0 =
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bl_mem_params->ep_info.args.arg1;
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bl_mem_params->ep_info.args.arg1 = 0;
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if (hw_cfg_mem_params)
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bl_mem_params->ep_info.args.arg2 =
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hw_cfg_mem_params->image_info.image_base;
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else
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bl_mem_params->ep_info.args.arg2 = 0;
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bl_mem_params->ep_info.args.arg3 = 0;
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bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry();
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break;
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case BL33_IMAGE_ID:
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/* AArch32 only core: OP-TEE expects NSec EP in register LR */
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pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
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assert(pager_mem_params);
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pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry();
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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void bl2_el3_plat_arch_setup(void)
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{
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/* Setup the MMU here */
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}
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#define WARP7_UART1_TX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
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#define WARP7_UART1_TX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4)
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#define WARP7_UART1_RX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA
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#define WARP7_UART1_RX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4)
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#define WARP7_UART6_TX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA
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#define WARP7_UART6_TX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4)
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#define WARP7_UART6_RX_MUX \
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IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA
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#define WARP7_UART6_RX_FEATURES \
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(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \
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IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
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static void warp7_setup_pinmux(void)
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{
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/* Configure UART1 TX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET,
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WARP7_UART1_TX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET,
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WARP7_UART1_TX_FEATURES);
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/* Configure UART1 RX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET,
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WARP7_UART1_RX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET,
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WARP7_UART1_RX_FEATURES);
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/* Configure UART6 TX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET,
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WARP7_UART6_TX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET,
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WARP7_UART6_TX_FEATURES);
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/* Configure UART6 RX */
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imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET,
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WARP7_UART6_RX_MUX);
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imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET,
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WARP7_UART6_RX_FEATURES);
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}
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static void warp7_usdhc_setup(void)
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{
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imx_usdhc_params_t params;
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struct mmc_device_info info;
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zeromem(¶ms, sizeof(imx_usdhc_params_t));
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params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
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params.clk_rate = 25000000;
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params.bus_width = MMC_BUS_WIDTH_8;
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info.mmc_dev_type = MMC_IS_EMMC;
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imx_usdhc_init(¶ms, &info);
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}
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static void warp7_setup_system_counter(void)
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{
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unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
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/* Set the frequency table index to our target frequency */
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write_cntfrq(freq);
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/* Enable system counter @ frequency table index 0, halt on debug */
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mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
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}
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static void warp7_setup_wdog_clocks(void)
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{
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uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT;
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imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
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imx_clock_enable_wdog(0);
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imx_clock_enable_wdog(1);
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imx_clock_enable_wdog(2);
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imx_clock_enable_wdog(3);
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}
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static void warp7_setup_usb_clocks(void)
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{
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uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
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imx_clock_set_usb_clk_root_bits(usb_en_bits);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
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imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
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}
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/*
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* bl2_early_platform_setup()
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* MMU off
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*/
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void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
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u_register_t arg3, u_register_t arg4)
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{
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uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
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uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
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uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
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/* Initialize the AIPS */
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imx_aips_init();
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imx_csu_init();
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imx_snvs_init();
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imx_gpt_ops_init(GPT1_BASE_ADDR);
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/* Initialize clocks, regulators, pin-muxes etc */
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imx_clock_init();
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imx_clock_enable_uart(0, uart1_en_bits);
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imx_clock_enable_uart(5, uart6_en_bits);
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imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
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warp7_setup_system_counter();
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warp7_setup_wdog_clocks();
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warp7_setup_usb_clocks();
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/* Setup pin-muxes */
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warp7_setup_pinmux();
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/* Init UART, storage and friends */
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console_init(PLAT_WARP7_BOOT_UART_BASE, PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
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PLAT_WARP7_CONSOLE_BAUDRATE);
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warp7_usdhc_setup();
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/* Open handles to persistent storage */
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plat_warp7_io_setup();
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/* Setup higher-level functionality CAAM, RTC etc */
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imx_caam_init();
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imx_wdog_init();
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/* Print out the expected memory map */
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VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT);
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VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
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VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
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VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT);
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VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT);
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VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT);
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}
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/*
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* bl2_platform_setup()
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* MMU on - enabled by bl2_el3_plat_arch_setup()
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*/
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void bl2_platform_setup(void)
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{
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}
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