184 lines
5.1 KiB
ArmAsm
184 lines
5.1 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_data.h>
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#include <cpu_macros.S>
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#if IMAGE_BL1 || IMAGE_BL32
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/*
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* The reset handler common to all platforms. After a matching
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* cpu_ops structure entry is found, the correponding reset_handler
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* in the cpu_ops is invoked. The reset handler is invoked very early
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* in the boot sequence and it is assumed that we can clobber r0 - r10
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* without the need to follow AAPCS.
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* Clobbers: r0 - r10
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*/
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.globl reset_handler
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func reset_handler
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mov r10, lr
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/* The plat_reset_handler can clobber r0 - r9 */
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bl plat_reset_handler
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/* Get the matching cpu_ops pointer (clobbers: r0 - r5) */
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bl get_cpu_ops_ptr
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#if ASM_ASSERTION
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops reset handler */
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ldr r1, [r0, #CPU_RESET_FUNC]
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cmp r1, #0
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mov lr, r10
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bxne r1
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bx lr
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endfunc reset_handler
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#endif /* IMAGE_BL1 || IMAGE_BL32 */
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#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
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/*
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* The prepare core power down function for all platforms. After
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* the cpu_ops pointer is retrieved from cpu_data, the corresponding
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* pwr_dwn_core in the cpu_ops is invoked. Follows AAPCS.
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*/
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.globl prepare_core_pwr_dwn
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func prepare_core_pwr_dwn
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push {lr}
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bl _cpu_data
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pop {lr}
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ASM_ASSERTION
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cmp r1, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops core_pwr_dwn handler */
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ldr r0, [r1, #CPU_PWR_DWN_CORE]
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bx r0
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endfunc prepare_core_pwr_dwn
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/*
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* The prepare cluster power down function for all platforms. After
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* the cpu_ops pointer is retrieved from cpu_data, the corresponding
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* pwr_dwn_cluster in the cpu_ops is invoked. Follows AAPCS.
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*/
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.globl prepare_cluster_pwr_dwn
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func prepare_cluster_pwr_dwn
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push {lr}
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bl _cpu_data
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pop {lr}
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ASM_ASSERTION
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cmp r1, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops cluster_pwr_dwn handler */
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ldr r0, [r1, #CPU_PWR_DWN_CLUSTER]
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bx r0
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endfunc prepare_cluster_pwr_dwn
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/*
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* Initializes the cpu_ops_ptr if not already initialized
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* in cpu_data. This must only be called after the data cache
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* is enabled. AAPCS is followed.
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*/
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.globl init_cpu_ops
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func init_cpu_ops
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push {r4 - r6, lr}
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bl _cpu_data
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mov r6, r0
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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cmp r1, #0
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bne 1f
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bl get_cpu_ops_ptr
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#if ASM_ASSERTION
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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str r0, [r6, #CPU_DATA_CPU_OPS_PTR]!
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1:
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pop {r4 - r6, pc}
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endfunc init_cpu_ops
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#endif /* IMAGE_BL32 */
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/*
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* The below function returns the cpu_ops structure matching the
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* midr of the core. It reads the MIDR and finds the matching
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* entry in cpu_ops entries. Only the implementation and part number
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* are used to match the entries.
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* Return :
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* r0 - The matching cpu_ops pointer on Success
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* r0 - 0 on failure.
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* Clobbers: r0 - r5
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*/
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.globl get_cpu_ops_ptr
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func get_cpu_ops_ptr
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/* Get the cpu_ops start and end locations */
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ldr r4, =(__CPU_OPS_START__ + CPU_MIDR)
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ldr r5, =(__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov r0, #0
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/* Read the MIDR_EL1 */
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ldcopr r2, MIDR
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ldr r3, =CPU_IMPL_PN_MASK
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/* Retain only the implementation and part number using mask */
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and r2, r2, r3
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1:
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/* Check if we have reached end of list */
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cmp r4, r5
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bge error_exit
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/* load the midr from the cpu_ops */
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ldr r1, [r4], #CPU_OPS_SIZE
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and r1, r1, r3
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/* Check if midr matches to midr of this core */
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cmp r1, r2
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bne 1b
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/* Subtract the increment and offset to get the cpu-ops pointer */
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sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR)
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error_exit:
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bx lr
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endfunc get_cpu_ops_ptr
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