127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <pubsub.h>
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#include <sve.h>
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static void *disable_sve_hook(const void *arg)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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/*
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* Disable SVE, SIMD and FP access for the Secure world.
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* As the SIMD/FP registers are part of the SVE Z-registers, any
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* use of SIMD/FP functionality will corrupt the SVE registers.
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* Therefore it is necessary to prevent use of SIMD/FP support
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* in the Secure world as well as SVE functionality.
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*/
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cptr = read_cptr_el3();
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cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT);
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write_cptr_el3(cptr);
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/*
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* No explicit ISB required here as ERET to switch to Secure
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* world covers it
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*/
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}
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return 0;
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}
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static void *enable_sve_hook(const void *arg)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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/*
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* Enable SVE, SIMD and FP access for the Non-secure world.
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*/
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cptr = read_cptr_el3();
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cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT);
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write_cptr_el3(cptr);
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/*
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* No explicit ISB required here as ERET to switch to Non-secure
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* world covers it
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*/
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}
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return 0;
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}
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void sve_enable(int el2_unused)
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{
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uint64_t features;
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features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT;
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if ((features & ID_AA64PFR0_SVE_MASK) == 1) {
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uint64_t cptr;
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#if CTX_INCLUDE_FPREGS
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/*
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* CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
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*/
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assert(0);
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#endif
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/*
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* Update CPTR_EL3 to enable access to SVE functionality for the
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* Non-secure world.
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* NOTE - assumed that CPTR_EL3.TFP is set to allow access to
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* the SIMD, floating-point and SVE support.
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*
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* CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality
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* in the Non-secure world.
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*/
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cptr = read_cptr_el3();
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cptr |= CPTR_EZ_BIT;
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write_cptr_el3(cptr);
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/*
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* Need explicit ISB here to guarantee that update to ZCR_ELx
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* and CPTR_EL2.TZ do not result in trap to EL3.
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*/
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isb();
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/*
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* Ensure lower ELs have access to full vector length.
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*/
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write_zcr_el3(ZCR_EL3_LEN_MASK);
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if (el2_unused) {
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/*
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* Update CPTR_EL2 to enable access to SVE functionality
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* for Non-secure world, EL2 and Non-secure EL1 and EL0.
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* NOTE - assumed that CPTR_EL2.TFP is set to allow
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* access to the SIMD, floating-point and SVE support.
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*
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* CPTR_EL2.TZ: Set to 0 to enable access to SVE support
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* for EL2 and Non-secure EL1 and EL0.
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*/
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cptr = read_cptr_el2();
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cptr &= ~(CPTR_EL2_TZ_BIT);
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write_cptr_el2(cptr);
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/*
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* Ensure lower ELs have access to full vector length.
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*/
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write_zcr_el2(ZCR_EL2_LEN_MASK);
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}
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/*
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* No explicit ISB required here as ERET to switch to
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* Non-secure world covers it.
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*/
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}
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}
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SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
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SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook);
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