96 lines
3.7 KiB
C
96 lines
3.7 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __XLAT_TABLES_ARCH_H__
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#define __XLAT_TABLES_ARCH_H__
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#include <arch.h>
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#include <platform_def.h>
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#include <xlat_tables_defs.h>
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/*
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* In AArch32 state, the MMU only supports 4KB page granularity, which means
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* that the first translation table level is either 1 or 2. Both of them are
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* allowed to have block and table descriptors. See section G4.5.6 of the
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* ARMv8-A Architecture Reference Manual (DDI 0487A.k) for more information.
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*
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* The define below specifies the first table level that allows block
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* descriptors.
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*/
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#define MIN_LVL_BLOCK_DESC 1
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/*
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* Each platform can define the size of the virtual address space, which is
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* defined in PLAT_VIRT_ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus
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* the width of said address space. The value of TTBCR.TxSZ must be in the
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* range 0 to 7 [1], which means that the virtual address space width must be
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* in the range 32 to 25 bits.
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*
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* Here we calculate the initial lookup level from the value of
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* PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 1 supports virtual
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* address spaces of widths 32 to 31 bits, and level 2 from 30 to 25. Wider or
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* narrower address spaces are not supported. As a result, level 3 cannot be
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* used as initial lookup level with 4 KB granularity [1].
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*
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* For example, for a 31-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
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* 1 << 31), TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table
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* G4-5 in the ARM ARM, the initial lookup level for an address space like that
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* is 1.
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*
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* See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
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* information:
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* [1] Section G4.6.5
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*/
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#if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN))
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
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#elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
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# define XLAT_TABLE_LEVEL_BASE 1
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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#elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX))
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# define XLAT_TABLE_LEVEL_BASE 2
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# define NUM_BASE_LEVEL_ENTRIES \
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(PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
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#else
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# error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
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#endif
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#endif /* __XLAT_TABLES_ARCH_H__ */
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