160 lines
3.5 KiB
C
160 lines
3.5 KiB
C
/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <lib/smccc.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <services/arm_arch_svc.h>
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return BL33_BASE;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return read_cntfrq_el0();
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}
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static uintptr_t boot_ctx_address;
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static uint16_t boot_itf_selected;
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void stm32mp_save_boot_ctx_address(uintptr_t address)
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{
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boot_api_context_t *boot_context = (boot_api_context_t *)address;
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boot_ctx_address = address;
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boot_itf_selected = boot_context->boot_interface_selected;
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}
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uintptr_t stm32mp_get_boot_ctx_address(void)
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{
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return boot_ctx_address;
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}
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uint16_t stm32mp_get_boot_itf_selected(void)
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{
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return boot_itf_selected;
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}
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uintptr_t stm32mp_ddrctrl_base(void)
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{
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return DDRCTRL_BASE;
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}
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uintptr_t stm32mp_ddrphyc_base(void)
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{
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return DDRPHYC_BASE;
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}
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uintptr_t stm32mp_pwr_base(void)
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{
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return PWR_BASE;
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}
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uintptr_t stm32mp_rcc_base(void)
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{
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return RCC_BASE;
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}
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bool stm32mp_lock_available(void)
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{
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const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
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/* The spinlocks are used only when MMU and data cache are enabled */
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return (read_sctlr() & c_m_bits) == c_m_bits;
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}
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#if STM32MP_USE_STM32IMAGE
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int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
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{
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uint32_t i;
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uint32_t img_checksum = 0U;
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/*
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* Check header/payload validity:
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* - Header magic
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* - Header version
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* - Payload checksum
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*/
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if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
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ERROR("Header magic\n");
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return -EINVAL;
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}
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if (header->header_version != BOOT_API_HEADER_VERSION) {
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ERROR("Header version\n");
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return -EINVAL;
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}
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for (i = 0U; i < header->image_length; i++) {
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img_checksum += *(uint8_t *)(buffer + i);
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}
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if (header->payload_checksum != img_checksum) {
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ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum,
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header->payload_checksum);
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return -EINVAL;
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}
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return 0;
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}
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#endif /* STM32MP_USE_STM32IMAGE */
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int stm32mp_map_ddr_non_cacheable(void)
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{
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return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE,
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MT_NON_CACHEABLE | MT_RW | MT_SECURE);
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}
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int stm32mp_unmap_ddr(void)
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{
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return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE);
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}
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/*****************************************************************************
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* plat_is_smccc_feature_available() - This function checks whether SMCCC
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* feature is availabile for platform.
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* @fid: SMCCC function id
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*
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* Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
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* SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
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*****************************************************************************/
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int32_t plat_is_smccc_feature_available(u_register_t fid)
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{
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switch (fid) {
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case SMCCC_ARCH_SOC_ID:
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return SMC_ARCH_CALL_SUCCESS;
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default:
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return SMC_ARCH_CALL_NOT_SUPPORTED;
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}
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}
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/* Get SOC version */
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int32_t plat_get_soc_version(void)
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{
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uint32_t chip_id = stm32mp_get_chip_dev_id();
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uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
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return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
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}
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/* Get SOC revision */
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int32_t plat_get_soc_revision(void)
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{
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return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
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}
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