Varun Wadekar b42192bcbd Tegra210: wait for 512 timer ticks before retention entry ... This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers, so that the core waits for 512 generic timer CNTVALUEB ticks before entering retention state, after executing a WFI instruction. This functionality is configurable and can be enabled for platforms by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and 'ENABLE_CPU_DYNAMIC_RETENTION' flag. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2015-08-24 21:34:28 +05:30
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plat_psci_handlers.c	Tegra210: enable WRAP to INCR burst type conversions	2015-07-27 17:34:41 +05:30
plat_secondary.c	Tegra210: lock PMC registers holding CPU vector addresses	2015-07-17 19:06:54 +05:30
plat_setup.c	Support for NVIDIA's Tegra T210 SoCs	2015-05-29 16:43:25 +05:30
platform_t210.mk	Tegra210: wait for 512 timer ticks before retention entry	2015-08-24 21:34:28 +05:30