86 lines
2.1 KiB
Makefile
86 lines
2.1 KiB
Makefile
#
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# Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include common/fdt_wrappers.mk
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# platform configs
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ENABLE_CONSOLE_SPE := 1
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$(eval $(call add_define,ENABLE_CONSOLE_SPE))
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ENABLE_STRICT_CHECKING_MODE := 1
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$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
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USE_GPC_DMA := 1
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$(eval $(call add_define,USE_GPC_DMA))
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RESET_TO_BL31 := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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COLD_BOOT_SINGLE_CPU := 1
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# platform settings
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TZDRAM_BASE := 0x40000000
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$(eval $(call add_define,TZDRAM_BASE))
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MAX_XLAT_TABLES := 25
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$(eval $(call add_define,MAX_XLAT_TABLES))
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MAX_MMAP_REGIONS := 30
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$(eval $(call add_define,MAX_MMAP_REGIONS))
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# enable RAS handling
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HANDLE_EA_EL3_FIRST := 1
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RAS_EXTENSION := 1
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# platform files
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PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
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-I${SOC_DIR}/drivers/include
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BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
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drivers/ti/uart/aarch64/16550_console.S \
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lib/cpus/aarch64/denver.S \
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${TEGRA_DRIVERS}/bpmp_ipc/intf.c \
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${TEGRA_DRIVERS}/bpmp_ipc/ivc.c \
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${TEGRA_DRIVERS}/memctrl/memctrl_v2.c \
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${TEGRA_DRIVERS}/smmu/smmu.c \
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${SOC_DIR}/drivers/mce/mce.c \
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${SOC_DIR}/drivers/mce/nvg.c \
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${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
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${SOC_DIR}/drivers/se/se.c \
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${SOC_DIR}/plat_memctrl.c \
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${SOC_DIR}/plat_psci_handlers.c \
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${SOC_DIR}/plat_setup.c \
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${SOC_DIR}/plat_secondary.c \
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${SOC_DIR}/plat_sip_calls.c \
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${SOC_DIR}/plat_smmu.c \
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${SOC_DIR}/plat_trampoline.S
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ifeq (${USE_GPC_DMA}, 1)
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BL31_SOURCES += ${TEGRA_DRIVERS}/gpcdma/gpcdma.c
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endif
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ifeq (${ENABLE_CONSOLE_SPE},1)
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BL31_SOURCES += ${TEGRA_DRIVERS}/spe/shared_console.S
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endif
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# RAS sources
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ifeq (${RAS_EXTENSION},1)
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BL31_SOURCES += lib/extensions/ras/std_err_record.c \
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lib/extensions/ras/ras_common.c \
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${SOC_DIR}/plat_ras.c
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endif
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# SPM dispatcher
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ifeq (${SPD},spmd)
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include lib/libfdt/libfdt.mk
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# sources to support spmd
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BL31_SOURCES += plat/common/plat_spmd_manifest.c \
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${LIBFDT_SRCS}
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BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
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endif
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