24 lines
855 B
C
24 lines
855 B
C
/*
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* Copyright (c) 2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_MATTERHORN_H
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#define CORTEX_MATTERHORN_H
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#define CORTEX_MATTERHORN_MIDR U(0x410FD470)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_MATTERHORN_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_MATTERHORN_H */
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