118 lines
4.5 KiB
C
118 lines
4.5 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arm_def.h>
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#include <gicv3.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <platform_def.h>
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/******************************************************************************
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* The following functions are defined as weak to allow a platform to override
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* the way the GICv3 driver is initialised and used.
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*****************************************************************************/
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#pragma weak plat_arm_gic_driver_init
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#pragma weak plat_arm_gic_init
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#pragma weak plat_arm_gic_cpuif_enable
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#pragma weak plat_arm_gic_cpuif_disable
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#pragma weak plat_arm_gic_pcpu_init
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/* The GICv3 driver only needs to be initialized in EL3 */
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static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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/* Array of Group1 secure interrupts to be configured by the gic driver */
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static const unsigned int g1s_interrupt_array[] = {
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PLAT_ARM_G1S_IRQS
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};
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/* Array of Group0 interrupts to be configured by the gic driver */
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static const unsigned int g0_interrupt_array[] = {
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PLAT_ARM_G0_IRQS
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};
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const gicv3_driver_data_t arm_gic_data = {
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.gicd_base = PLAT_ARM_GICD_BASE,
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.gicr_base = PLAT_ARM_GICR_BASE,
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.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
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.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
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.g0_interrupt_array = g0_interrupt_array,
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.g1s_interrupt_array = g1s_interrupt_array,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = plat_arm_calc_core_pos
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};
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void plat_arm_gic_driver_init(void)
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{
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/*
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* The GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in SEL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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#if IMAGE_BL31
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gicv3_driver_init(&arm_gic_data);
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#endif
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}
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/******************************************************************************
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* ARM common helper to initialize the GIC. Only invoked by BL31
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*****************************************************************************/
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void plat_arm_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to enable the GIC CPU interface
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*****************************************************************************/
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void plat_arm_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to disable the GIC CPU interface
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*****************************************************************************/
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void plat_arm_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to initialize the per-cpu redistributor interface in GICv3
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*****************************************************************************/
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void plat_arm_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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