Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF. This patch changes the search criteria, to look for this marker, to calculate the size of the saved context. Change-Id: I15d91945ecb78267f91c45f37985dbb2327ca3ae Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
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smmu.c |