Konstantin Porotchkin bc6206f7f6 lib: cpu: Add L2 cache aux control register definition to CA72 ... Add definition of EL1 L2 Auxilary Control register to Cortex A72 library headers. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>		2018-07-18 18:48:30 +03:00
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aarch32	aarch32: Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
aarch64	lib: cpu: Add L2 cache aux control register definition to CA72	2018-07-18 18:48:30 +03:00
errata_report.h	Fix MISRA rule 8.4 in common code	2018-02-28 17:18:46 +00:00
wa_cve_2017_5715.h	Rename symbols and files relating to CVE-2017-5715	2018-05-23 12:45:48 +01:00
wa_cve_2018_3639.h	Add support for dynamic mitigation for CVE-2018-3639	2018-05-23 12:45:48 +01:00