60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <gicv2.h>
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#include <plat_marvell.h>
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#include <platform.h>
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#include <platform_def.h>
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/*
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* The following functions are defined as weak to allow a platform to override
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* the way the GICv2 driver is initialised and used.
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*/
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#pragma weak plat_marvell_gic_driver_init
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#pragma weak plat_marvell_gic_init
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/*
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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*/
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static const interrupt_prop_t marvell_interrupt_props[] = {
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PLAT_MARVELL_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
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PLAT_MARVELL_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
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};
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static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
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/*
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* Ideally `marvell_gic_data` structure definition should be a `const` but it is
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* kept as modifiable for overwriting with different GICD and GICC base when
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* running on FVP with VE memory map.
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*/
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static gicv2_driver_data_t marvell_gic_data = {
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.gicd_base = PLAT_MARVELL_GICD_BASE,
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.gicc_base = PLAT_MARVELL_GICC_BASE,
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.interrupt_props = marvell_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(marvell_interrupt_props),
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.target_masks = target_mask_array,
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.target_masks_num = ARRAY_SIZE(target_mask_array),
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};
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/*
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* ARM common helper to initialize the GICv2 only driver.
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*/
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void plat_marvell_gic_driver_init(void)
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{
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gicv2_driver_init(&marvell_gic_data);
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}
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void plat_marvell_gic_init(void)
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{
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_set_pe_target_mask(plat_my_core_pos());
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gicv2_cpuif_enable();
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}
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