johpow01 62bbfe82c8 Workaround for Cortex A77 erratum 1800714 ... Cortex A77 erratum 1800714 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. Since this is the first errata workaround implemented for Cortex A77, this patch also adds the required cortex_a77_reset_func in the file lib/cpus/aarch64/cortex_a77.S. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I844de34ee1bd0268f80794e2d9542de2f30fd3ad		2020-06-25 14:50:58 +00:00
..
aarch32	Cortex A9:errata 794073 workaround	2019-04-12 10:10:32 +00:00
aarch64	Workaround for Cortex A77 erratum 1800714	2020-06-25 14:50:58 +00:00
cpu-ops.mk	Workaround for Cortex A77 erratum 1800714	2020-06-25 14:50:58 +00:00
errata_report.c	Coverity: remove unnecessary header file includes	2020-02-04 10:23:51 -06:00