26e9984186
The communication protocol used between the AP cores and the SCP
has undergone a number of changes. This patch makes the required
modifications to the SCP Boot Protocol, SCPI Protocol and MHU
driver code in the Juno platform code so that the AP cores are
still able to communicate with the SCP.
This patch focuses on the mandatory changes to make it work. The
design of this code needs to be improved but this will come in
a subsequent patch.
The main changes are:
- MHU communication protocol
- The command ID and payload size are no longer written into the
MHU registers directly. Instead, they are stored in the payload
area. The MHU registers are now used only as a doorbell to kick
off messages. Same goes for any command result, the AP has to
pick it up from the payload area.
- SCP Boot Protocol
- The BL3-0 image is now expected to embed a checksum. This
checksum must be passed to the SCP, which uses it to check the
integrity of the image it received.
- On Juno, the BL3-0 image used to be transferred a block (4KB)
at a time. The SCP now supports receiving up to 128KB at a
time, which is more than the size of the BL3-0 image.
Therefore, the image is now sent in one go.
- The command IDs have changed.
- SCPI Protocol
- On Juno, the size of the SCPI payload has been reduced down
from 512 bytes to 256 bytes. This changes the base address
of the AP-to-SCP payload area.
- For commands that have a response, the response is the same SCPI
header that was sent, except for the size and the status, which
both must be updated appropriately. Success/Failure of a command
is determined by looking at the updated status code.
- Some command IDs have changed.
NOTE: THIS PATCH BREAKS COMPATIBILITY WITH FORMER VERSIONS OF THE SCP
FIRMWARE AND THUS REQUIRES AN UPDATE OF THIS BINARY. THE LATEST SCP
BINARY CAN BE OBTAINED FROM ARM CONNECTED COMMUNITY WEBSITE.
Change-Id: Ia5f6b95fe32401ee04a3805035748e8ef6718da7
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| bl2 | ||
| bl31 | ||
| bl32/tsp | ||
| common | ||
| docs | ||
| drivers | ||
| fdts | ||
| include | ||
| lib | ||
| plat | ||
| services | ||
| tools | ||
| .gitignore | ||
| Makefile | ||
| acknowledgements.md | ||
| contributing.md | ||
| license.md | ||
| readme.md | ||
readme.md
ARM Trusted Firmware - version 1.1
ARM Trusted Firmware provides a reference implementation of secure world software for ARMv8-A, including Exception Level 3 (EL3) software. This release provides complete support for version 0.2 of the PSCI specification, initial support for the new version 1.0 of that specification, and prototype support for the Trusted Board Boot Requirements specification.
The intent is to provide a reference implementation of various ARM interface standards, such as the Power State Coordination Interface (PSCI), Trusted Board Boot Requirements (TBBR) and [Secure Monitor] TEE-SMC code. As far as possible the code is designed for reuse or porting to other ARMv8-A model and hardware platforms.
ARM will continue development in collaboration with interested parties to provide a full reference implementation of PSCI, TBBR and Secure Monitor code to the benefit of all developers working with ARMv8-A TrustZone technology.
License
The software is provided under a BSD 3-Clause license. Certain source files are derived from FreeBSD code: the original license is included in these source files.
This Release
This release is a limited functionality implementation of the Trusted Firmware. It provides a suitable starting point for productization. Future versions will contain new features, optimizations and quality improvements.
Functionality
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Prototype implementation of a subset of the Trusted Board Boot Requirements Platform Design Document (PDD). This includes packaging the various firmware images into a Firmware Image Package (FIP) to be loaded from non-volatile storage, and a prototype of authenticated boot using key certificates stored in the FIP.
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Initializes the secure world (for example, exception vectors, control registers, GIC and interrupts for the platform), before transitioning into the normal world.
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Supports both GICv2 and GICv3 initialization for use by normal world software.
-
Starts the normal world at the Exception Level and Register Width specified by the platform port. Typically this is AArch64 EL2 if available.
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Handles SMCs (Secure Monitor Calls) conforming to the [SMC Calling Convention PDD] SMCCC using an EL3 runtime services framework.
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Handles SMCs relating to the [Power State Coordination Interface PDD] PSCI for the Secondary CPU Boot, CPU Hotplug, CPU Idle and System Shutdown/Reset use-cases.
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A Test Secure-EL1 Payload and Dispatcher to demonstrate Secure Monitor functionality such as world switching, EL1 context management and interrupt routing. This also demonstrates Secure-EL1 interaction with PSCI. Some of this functionality is provided in library form for re-use by other Secure-EL1 Payload Dispatchers.
-
Support for alternative Trusted Boot Firmware. Some platforms have their own Trusted Boot implementation and only require the Secure Monitor functionality provided by ARM Trusted Firmware.
-
Isolation of memory accessible by the secure world from the normal world through programming of a TrustZone controller.
-
Support for CPU specific reset sequences, power down sequences and register dumping during crash reporting. The CPU specific reset sequences include support for errata workarounds.
For a full description of functionality and implementation details, please see the Firmware Design and supporting documentation. The Change Log provides details of changes made since the last release.
Platforms
This release of the Trusted Firmware has been tested on Revision B of the [Juno ARM Development Platform] Juno with Version r0p0-00rel7 of the [ARM SCP Firmware] SCP download.
The Trusted Firmware has also been tested on the 64-bit Linux versions of the following ARM FVPs:
Foundation_Platform(Version 9.1, Build 9.1.33)FVP_Base_AEMv8A-AEMv8A(Version 6.2, Build 0.8.6202)FVP_Base_Cortex-A57x4-A53x4(Version 6.2, Build 0.8.6202)FVP_Base_Cortex-A57x1-A53x1(Version 6.2, Build 0.8.6202)FVP_Base_Cortex-A57x2-A53x4(Version 6.2, Build 0.8.6202)
The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM: see [www.arm.com/fvp] FVP.
Still to Come
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Complete and more flexible Trusted Board Boot implementation.
-
Complete implementation of the PSCI v1.0 specification.
-
Support for alternative types of Secure-EL1 Payloads.
-
Extending the GICv3 support to the secure world.
-
Support for new System IP devices.
For a full list of detailed issues in the current code, please see the Change Log and the GitHub issue tracker.
Getting Started
Get the Trusted Firmware source code from GitHub.
See the User Guide for instructions on how to install, build and use the Trusted Firmware with the ARM FVPs.
See the Firmware Design for information on how the ARM Trusted Firmware works.
See the Porting Guide as well for information about how to use this software on another ARMv8-A platform.
See the Contributing Guidelines for information on how to contribute to this project and the Acknowledgments file for a list of contributors to the project.
Feedback and support
ARM welcomes any feedback on the Trusted Firmware. Please send feedback using the GitHub issue tracker.
ARM licensees may contact ARM directly via their partner managers.
Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.