Tien Hock Loh aea772dd7a plat: intel: set DRVSEL and SMPLSEL for DWMMC ... DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677		2020-06-08 22:03:34 +00:00
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agilex_clock_manager.h	plat: intel: set DRVSEL and SMPLSEL for DWMMC	2020-06-08 22:03:34 +00:00
agilex_memory_controller.h	intel: Enable bridge access in Intel platform	2020-01-16 10:53:21 +08:00
agilex_mmc.h	plat: intel: set DRVSEL and SMPLSEL for DWMMC	2020-06-08 22:03:34 +00:00
agilex_noc.h	intel: Adds support for Agilex platform	2019-07-17 19:06:49 +08:00
agilex_pinmux.h	intel: Refactor common platform code [1/5]	2019-11-28 12:47:57 +08:00
socfpga_plat_def.h	intel: Change boot source selection	2020-02-03 14:31:52 +08:00