arm-trusted-firmware/plat/nvidia/tegra/include/drivers
Jeetesh Burman 4eed9c8480 Tegra186: add SE support to generate SHA256 of TZRAM
The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
2020-03-09 15:25:16 -07:00
..
bpmp.h Tegra: bpmp: mark device "not present" on boot timeout 2019-01-31 08:50:31 -08:00
bpmp_ipc.h Tegra: include: fix violations of MISRA Rule 21.1 2020-01-12 14:44:40 -08:00
flowctrl.h Tegra: support for System Suspend using sc7entry-fw binary 2019-01-31 08:48:36 -08:00
gpcdma.h Tegra: include: fix violations of MISRA Rule 21.1 2020-01-12 14:44:40 -08:00
mce.h Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
memctrl.h Tegra: memctrl: clean MC INT status before exit to bootloader 2019-01-18 09:21:51 -08:00
memctrl_v1.h Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
memctrl_v2.h Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ 2019-08-01 13:14:12 -07:00
pmc.h Tegra210: update the PMC blacklisted registers 2020-03-09 15:25:15 -07:00
security_engine.h Tegra186: add SE support to generate SHA256 of TZRAM 2020-03-09 15:25:16 -07:00
smmu.h Tegra186: smmu: add support for backup multiple smmu regs 2019-01-31 08:45:22 -08:00
spe.h spe: Use generic console_t data structure 2020-02-25 09:34:38 +00:00
tegra_gic.h Tegra: include: fix violations of MISRA Rule 21.1 2020-01-12 14:44:40 -08:00