Pravin a69a30ff23 Tegra194: memctrl: add support for MIU4 and MIU5 ... This patch adds support for memqual miu 4,5. The MEMQUAL engine has miu0 to miu7 in which miu6 and miu7 is hardwired to bypass SMMU. So only miu0 to miu5 support is provided. Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea Signed-off-by: Pravin <pt@nvidia.com>		2020-03-09 15:25:15 -07:00
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drivers	Tegra194: mce: declare nvg_roc_clean_cache_trbits()	2020-02-05 19:15:40 +00:00
plat_memctrl.c	Tegra194: memctrl: add support for MIU4 and MIU5	2020-03-09 15:25:15 -07:00
plat_psci_handlers.c	Tegra194: remove support for simulated system suspend	2020-01-31 13:21:46 -08:00
plat_secondary.c	Tegra194: helper functions for CPU rst handler and SMMU ctx offset	2019-11-28 11:14:21 -08:00
plat_setup.c	spe: Use generic console_t data structure	2020-02-25 09:34:38 +00:00
plat_sip_calls.c	Tegra194: remove support for simulated system suspend	2020-01-31 13:21:46 -08:00
plat_smmu.c	Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list	2020-01-23 09:03:01 -08:00
plat_trampoline.S	Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list	2020-01-23 09:03:01 -08:00
platform_t194.mk	Tegra194: enable spe-console functionality	2020-01-28 09:43:10 +00:00