96 lines
3.7 KiB
C
96 lines
3.7 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <debug.h>
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#include <mce.h>
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#include <mmio.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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#define MISCREG_CPU_RESET_VECTOR 0x2000
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#define MISCREG_AA64_RST_LOW 0x2004
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#define MISCREG_AA64_RST_HIGH 0x2008
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#define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658
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#define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C
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#define CPU_RESET_MODE_AA64 1
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t __tegra186_cpu_reset_handler_end;
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/*******************************************************************************
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* Setup secondary CPU vectors
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******************************************************************************/
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void plat_secondary_setup(void)
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{
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uint32_t addr_low, addr_high;
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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uint64_t cpu_reset_handler_base;
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INFO("Setting up secondary CPU boot\n");
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if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) &&
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(tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) {
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/*
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* The BL31 code resides in the TZSRAM which loses state
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* when we enter System Suspend. Copy the wakeup trampoline
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* code to TZDRAM to help us exit from System Suspend.
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*/
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cpu_reset_handler_base = params_from_bl2->tzdram_base;
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memcpy16((void *)((uintptr_t)cpu_reset_handler_base),
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(void *)(uintptr_t)tegra186_cpu_reset_handler,
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(uintptr_t)&__tegra186_cpu_reset_handler_end -
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(uintptr_t)tegra186_cpu_reset_handler);
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} else {
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cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint;
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}
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addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
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addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff);
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/* write lower 32 bits first, then the upper 11 bits */
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0,
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addr_low);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1,
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addr_high);
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/* update reset vector address to the CCPLEX */
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mce_update_reset_vector(addr_low, addr_high);
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}
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