395 lines
12 KiB
C
395 lines
12 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <plat/arm/board/common/v2m_def.h>
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#include <plat/arm/common/arm_spm_def.h>
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#include <plat/arm/common/smccc_def.h>
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#include <plat/common/common_def.h>
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#include <plat/arm/soc/common/soc_css_def.h>
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#define ARM_ROTPK_HEADER_LEN 19
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#define ARM_ROTPK_HASH_LEN 32
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
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/* PL011 UART related constants */
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#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
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#undef V2M_IOFPGA_UART0_CLK_IN_HZ
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#endif
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#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
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#undef V2M_IOFPGA_UART1_CLK_IN_HZ
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#endif
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#define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000
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#define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000
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/* Core/Cluster/Thread counts for corstone1000 */
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#define CORSTONE1000_CLUSTER_COUNT U(1)
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#define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4)
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#define CORSTONE1000_MAX_PE_PER_CPU U(1)
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#define CORSTONE1000_PRIMARY_CPU U(0)
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#define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT
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#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
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CORSTONE1000_MAX_CPUS_PER_CLUSTER * \
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CORSTONE1000_MAX_PE_PER_CPU)
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/* UART related constants */
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#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#define PLAT_ARM_RUN_UART_BASE 0x1a520000
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#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
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#define ARM_CONSOLE_BAUDRATE 115200
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
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/* Memory related constants */
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/* SRAM (CVM) memory layout
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*
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* <ARM_TRUSTED_SRAM_BASE>
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* partition size: sizeof(meminfo_t) = 16 bytes
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* content: memory info area used by the next BL
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*
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* <ARM_FW_CONFIG_BASE>
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* partition size: 4080 bytes
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*
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* <ARM_BL2_MEM_DESC_BASE>
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* partition size: 4 KB
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* content: Area where BL2 copies the images descriptors
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*
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* <ARM_BL_RAM_BASE> = <BL32_BASE>
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* partition size: 688 KB
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* content: BL32 (optee-os)
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*
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* <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
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* partition size: 8 KB
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* content: BL32 config (TOS_FW_CONFIG)
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*
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* <BL31_BASE>
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* partition size: 140 KB
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* content: BL31
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*
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* <BL2_SIGNATURE_BASE>
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* partition size: 4 KB
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* content: MCUBOOT data needed to verify TF-A BL2
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*
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* <BL2_BASE>
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* partition size: 176 KB
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* content: BL2
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*
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* <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
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* partition size: 512 KB
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* content: BL33 (u-boot)
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*/
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/* DDR memory */
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#define ARM_DRAM1_BASE UL(0x80000000)
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#define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1)
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/* DRAM1 and DRAM2 are the same for corstone1000 */
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#define ARM_DRAM2_BASE ARM_DRAM1_BASE
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#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE
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#define ARM_DRAM2_END ARM_DRAM1_END
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#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1)
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/* The first 8 KB of Trusted SRAM are used as shared memory */
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#define ARM_TRUSTED_SRAM_BASE UL(0x02000000)
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#define ARM_SHARED_RAM_SIZE (SZ_8K) /* 8 KB */
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#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
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/* The remaining Trusted SRAM is used to load the BL images */
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#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */
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/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
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#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K)
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#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \
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ARM_NS_SHARED_RAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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#define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */
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#define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */
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#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)
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#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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#define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */
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#define BL2_SIGNATURE_BASE (BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE)
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#define BL2_BASE (BL2_LIMIT - \
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PLAT_ARM_MAX_BL2_SIZE + \
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BL2_SIGNATURE_SIZE)
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#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#define BL31_BASE (BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE)
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#define BL31_LIMIT BL2_SIGNATURE_BASE
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#define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \
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CORSTONE1000_TOS_FW_CONFIG_SIZE)
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#define CORSTONE1000_TOS_FW_CONFIG_SIZE (SZ_8K) /* 8 KB */
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#define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE
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#define BL32_BASE ARM_BL_RAM_BASE
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#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE)
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#define BL32_LIMIT (BL32_BASE + PLAT_ARM_MAX_BL32_SIZE)
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/* SPD_spmd settings */
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#define PLAT_ARM_SPMC_BASE BL32_BASE
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#define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE
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/* NS memory */
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/* The last 512KB of the SRAM is allocated as shared memory */
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#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
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(PLAT_ARM_MAX_BL31_SIZE + \
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PLAT_ARM_MAX_BL32_SIZE))
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#define BL33_BASE ARM_DRAM1_BASE
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#define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/
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#define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
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/* end of the definition of SRAM memory layout */
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/* NOR Flash */
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#define PLAT_ARM_BOOT_BANK_FLAG UL(0x08002000)
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#define PLAT_ARM_FIP_BASE_BANK0 UL(0x081EF000)
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#define PLAT_ARM_FIP_BASE_BANK1 UL(0x0916F000)
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#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */
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#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE_BANK0
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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/*
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* Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
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* FW_CONFIG is intended to host the device tree. Currently, This area is not
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* used because corstone1000 platform doesn't use a device tree at TF-A level.
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*/
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#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t))
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#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \
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(ARM_SHARED_RAM_SIZE >> 1))
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/*
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* Boot parameters passed from BL2 to BL31/BL32 are stored here
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*/
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#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
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#define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE
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/*
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* The max number of regions like RO(code), coherent and data required by
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* different BL stages which need to be mapped in the MMU.
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*/
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#define ARM_BL_REGIONS 3
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#define PLAT_ARM_MMAP_ENTRIES 8
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#define MAX_XLAT_TABLES 5
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#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)
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#define MAX_IO_DEVICES 2
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#define MAX_IO_HANDLES 3
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#define MAX_IO_BLOCK_DEVICES 1
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE 0x1C010000
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#define PLAT_ARM_GICC_BASE 0x1C02F000
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/* MHUv2 Secure Channel receiver and sender */
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#define PLAT_SDK700_MHU0_SEND 0x1B800000
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#define PLAT_SDK700_MHU0_RECV 0x1B810000
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/* Timer/watchdog related constants */
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#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
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#define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
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#define ARM_SYS_TIMCTL_BASE UL(0x1a220000)
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#define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000
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#define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008
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#define SECURE_WATCHDOG_MASK_ENABLE 0x01
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#define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000
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#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */
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#define CORSTONE1000_IRQ_TZ_WDOG 32
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#define CORSTONE1000_IRQ_SEC_SYS_TIMER 34
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#define PLAT_MAX_PWR_LVL 2
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/*
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* Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
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* power levels have a 1:1 mapping with the MPIDR affinity levels.
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*/
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#define ARM_PWR_LVL0 MPIDR_AFFLVL0
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#define ARM_PWR_LVL1 MPIDR_AFFLVL1
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#define ARM_PWR_LVL2 MPIDR_AFFLVL2
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/*
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* Macros for local power states in ARM platforms encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define ARM_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define ARM_LOCAL_STATE_RET U(1)
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/* Local power state for OFF/power-down. Valid for CPU and cluster
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* power domains
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*/
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#define ARM_LOCAL_STATE_OFF U(2)
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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/*
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* This macro defines the deepest retention state possible. A higher state
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* ID will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE 1
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE 2
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#define PLATFORM_STACK_SIZE UL(0x440)
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#define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \
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PLAT_ARM_NVM_BASE, \
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PLAT_ARM_NVM_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
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ARM_SHARED_RAM_BASE, \
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ARM_SHARED_RAM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \
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ARM_NS_SHARED_RAM_BASE, \
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ARM_NS_SHARED_RAM_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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ARM_NS_DRAM1_BASE, \
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ARM_NS_DRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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(BL_CODE_END - BL_CODE_BASE), \
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MT_CODE | MT_SECURE), \
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MAP_REGION_FLAT( \
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BL_RO_DATA_BASE, \
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(BL_RO_DATA_END - BL_RO_DATA_BASE), \
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MT_RO_DATA | MT_SECURE)
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#if USE_COHERENT_MEM
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#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
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BL_COHERENT_RAM_BASE, \
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(BL_COHERENT_RAM_END \
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- BL_COHERENT_RAM_BASE), \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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/*
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* Map the region for the optional device tree configuration with read and
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* write permissions
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*/
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#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
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ARM_FW_CONFIG_BASE, \
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(ARM_FW_CONFIG_LIMIT \
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- ARM_FW_CONFIG_BASE), \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define CORSTONE1000_DEVICE_BASE (0x1A000000)
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#define CORSTONE1000_DEVICE_SIZE (0x26000000)
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#define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \
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CORSTONE1000_DEVICE_BASE, \
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CORSTONE1000_DEVICE_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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#define ARM_IRQ_SEC_SGI_0 8
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#define ARM_IRQ_SEC_SGI_1 9
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#define ARM_IRQ_SEC_SGI_2 10
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#define ARM_IRQ_SEC_SGI_3 11
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#define ARM_IRQ_SEC_SGI_4 12
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#define ARM_IRQ_SEC_SGI_5 13
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define ARM_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_EDGE)
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#define ARM_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
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GIC_INTR_CFG_EDGE)
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
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ARM_G1S_IRQ_PROPS(grp), \
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INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, \
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(grp), GIC_INTR_CFG_LEVEL)
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#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
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#endif /* PLATFORM_DEF_H */
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