Alexei Fedorov c3e8b0be9b AArch32: Disable Secure Cycle Counter ... This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>		2019-09-26 15:36:02 +00:00
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arch.h	AArch32: Disable Secure Cycle Counter	2019-09-26 15:36:02 +00:00
arch_features.h	drivers: generic_delay_timer: Assert presence of Generic Timer	2019-02-06 09:54:42 +00:00
arch_helpers.h	Cortex-A53: Workarounds for 819472, 824069 and 827319	2019-02-28 09:56:58 +00:00
asm_macros.S	Division functionality for cores that dont have divide hardware.	2019-02-19 17:07:48 +00:00
assert_macros.S	Reorganize architecture-dependent header files	2019-01-04 10:43:16 +00:00
console_macros.S	console: update skeleton	2019-07-16 13:01:02 +00:00
el3_common_macros.S	AArch32: Disable Secure Cycle Counter	2019-09-26 15:36:02 +00:00
smccc_helpers.h	Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__	2019-08-01 13:14:12 -07:00
smccc_macros.S	AArch32: Disable Secure Cycle Counter	2019-09-26 15:36:02 +00:00