27 lines
585 B
C
27 lines
585 B
C
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <mmio.h>
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#include <plat_common.h>
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void erratum_a010539(void)
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{
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if (get_boot_dev() == BOOT_DEVICE_QSPI) {
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unsigned int *porsr1 = (void *)(NXP_DCFG_ADDR +
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DCFG_PORSR1_OFFSET);
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uint32_t val;
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val = (gur_in32(porsr1) & ~PORSR1_RCW_MASK);
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mmio_write_32((uint32_t)(NXP_DCSR_DCFG_ADDR +
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DCFG_DCSR_PORCR1_OFFSET), htobe32(val));
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/* Erratum need to set '1' to all bits for reserved SCFG register 0x1a8 */
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mmio_write_32((uint32_t)(NXP_SCFG_ADDR + 0x1a8),
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htobe32(0xffffffff));
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}
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}
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