Caesar Wang 2831bc3a5f rockchip: add support save/restore configuration for DDR during enter S3 ... This patch intend to support save the registers of the DDR controller and PHY before suspend, and restore them after resume. Change-Id: Ia10b476c0b837628ac0f365416a7118292753e96 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>		2016-10-27 07:14:26 +08:00
..
dcf_code.inc	rockchip: rk3399: add dram driver	2016-08-25 08:37:42 +08:00
dfs.c	rockchip: Change dmc register accesses to ATF style for rk3399	2016-10-27 01:51:07 +08:00
dfs.h	rockchip: Break out common dram code for rk3399	2016-10-27 01:50:57 +08:00
dram.c	rockchip: Break out common dram code for rk3399	2016-10-27 01:50:57 +08:00
dram.h	rockchip: Break out common dram code for rk3399	2016-10-27 01:50:57 +08:00
dram_spec_timing.c	rockchip: Break out common dram code for rk3399	2016-10-27 01:50:57 +08:00
dram_spec_timing.h	rockchip: Break out common dram code for rk3399	2016-10-27 01:50:57 +08:00
suspend.c	rockchip: add support save/restore configuration for DDR during enter S3	2016-10-27 07:14:26 +08:00
suspend.h	rockchip: add support save/restore configuration for DDR during enter S3	2016-10-27 07:14:26 +08:00