375 lines
9.8 KiB
C
375 lines
9.8 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Driver for GIC-600AE Fault Management Unit
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*/
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#include <assert.h>
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#include <inttypes.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/arm/gic600ae_fmu.h>
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#include <drivers/arm/gicv3.h>
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/* GIC-600 AE FMU specific register offsets */
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/* GIC-600 AE FMU specific macros */
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#define FMU_ERRIDR_NUM U(44)
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#define FMU_ERRIDR_NUM_MASK U(0xFFFF)
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/* Safety mechanisms for GICD block */
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static char *gicd_sm_info[] = {
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"Reserved",
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"GICD dual lockstep error",
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"GICD AXI4 slave interface error",
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"GICD-PPI AXI4-Stream interface error",
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"GICD-ITS AXI4-Stream interface error",
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"GICD-SPI-Collator AXI4-Stream interface error",
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"GICD AXI4 master interface error",
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"SPI RAM DED error",
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"SGI RAM DED error",
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"Reserved",
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"LPI RAM DED error",
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"GICD-remote-GICD AXI4-Stream interface error",
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"GICD Q-Channel interface error",
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"GICD P-Channel interface error",
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"SPI RAM address decode error",
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"SGI RAM address decode error",
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"Reserved",
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"LPI RAM address decode error",
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"FMU dual lockstep error",
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"FMU ping ACK error",
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"FMU APB parity error",
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"GICD-Wake AXI4-Stream interface error",
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"GICD PageOffset or Chip ID error",
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"MBIST REQ error",
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"SPI RAM SEC error",
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"SGI RAM SEC error",
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"Reserved",
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"LPI RAM SEC error",
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"User custom SM0 error",
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"User custom SM1 error",
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"GICD-ITS Monolithic switch error",
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"GICD-ITS Q-Channel interface error",
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"GICD-ITS Monolithic interface error",
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"GICD FMU ClkGate override"
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};
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/* Safety mechanisms for PPI block */
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static char *ppi_sm_info[] = {
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"Reserved",
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"PPI dual lockstep error",
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"PPI-GICD AXI4-Stream interface error",
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"PPI-CPU-IF AXI4-Stream interface error",
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"PPI Q-Channel interface error",
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"PPI RAM DED error",
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"PPI RAM address decode error",
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"PPI RAM SEC error",
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"PPI User0 SM",
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"PPI User1 SM",
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"MBIST REQ error",
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"PPI interrupt parity protection error",
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"PPI FMU ClkGate override"
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};
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/* Safety mechanisms for ITS block */
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static char *its_sm_info[] = {
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"Reserved",
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"ITS dual lockstep error",
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"ITS-GICD AXI4-Stream interface error",
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"ITS AXI4 slave interface error",
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"ITS AXI4 master interface error",
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"ITS Q-Channel interface error",
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"ITS RAM DED error",
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"ITS RAM address decode error",
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"Bypass ACE switch error",
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"ITS RAM SEC error",
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"ITS User0 SM",
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"ITS User1 SM",
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"ITS-GICD Monolithic interface error",
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"MBIST REQ error",
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"ITS FMU ClkGate override"
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};
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/* Safety mechanisms for SPI Collator block */
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static char *spicol_sm_info[] = {
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"Reserved",
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"SPI Collator dual lockstep error",
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"SPI-Collator-GICD AXI4-Stream interface error",
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"SPI Collator Q-Channel interface error",
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"SPI Collator Q-Channel clock error",
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"SPI interrupt parity error"
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};
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/* Safety mechanisms for Wake Request block */
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static char *wkrqst_sm_info[] = {
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"Reserved",
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"Wake dual lockstep error",
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"Wake-GICD AXI4-Stream interface error"
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};
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/* Helper function to find detailed information for a specific IERR */
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static char __unused *ras_ierr_to_str(unsigned int blkid, unsigned int ierr)
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{
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char *str = NULL;
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/* Find the correct record */
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switch (blkid) {
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case FMU_BLK_GICD:
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assert(ierr < ARRAY_SIZE(gicd_sm_info));
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str = gicd_sm_info[ierr];
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break;
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case FMU_BLK_SPICOL:
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assert(ierr < ARRAY_SIZE(spicol_sm_info));
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str = spicol_sm_info[ierr];
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break;
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case FMU_BLK_WAKERQ:
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assert(ierr < ARRAY_SIZE(wkrqst_sm_info));
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str = wkrqst_sm_info[ierr];
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break;
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case FMU_BLK_ITS0...FMU_BLK_ITS7:
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assert(ierr < ARRAY_SIZE(its_sm_info));
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str = its_sm_info[ierr];
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break;
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case FMU_BLK_PPI0...FMU_BLK_PPI31:
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assert(ierr < ARRAY_SIZE(ppi_sm_info));
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str = ppi_sm_info[ierr];
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break;
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default:
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assert(false);
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break;
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}
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return str;
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}
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/*
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* Probe for error in memory-mapped registers containing error records.
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* Upon detecting an error, set probe data to the index of the record
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* in error, and return 1; otherwise, return 0.
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*/
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int gic600_fmu_probe(uint64_t base, int *probe_data)
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{
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uint64_t gsr;
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assert(base != 0UL);
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/*
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* Read ERR_GSR to find the error record 'M'
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*/
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gsr = gic_fmu_read_errgsr(base);
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if (gsr == U(0)) {
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return 0;
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}
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/* Return the index of the record in error */
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if (probe_data != NULL) {
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*probe_data = (int)__builtin_ctzll(gsr);
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}
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return 1;
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}
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/*
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* The handler function to read RAS records and find the safety
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* mechanism with the error.
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*/
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int gic600_fmu_ras_handler(uint64_t base, int probe_data)
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{
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uint64_t errstatus;
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unsigned int blkid = (unsigned int)probe_data, ierr, serr;
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assert(base != 0UL);
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/*
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* FMU_ERRGSR indicates the ID of the GIC
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* block that faulted.
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*/
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assert(blkid <= FMU_BLK_PPI31);
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/*
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* Find more information by reading FMU_ERR<M>STATUS
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* register
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*/
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errstatus = gic_fmu_read_errstatus(base, blkid);
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/*
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* If FMU_ERR<M>STATUS.V is set to 0, no RAS records
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* need to be scanned.
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*/
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if ((errstatus & FMU_ERRSTATUS_V_BIT) == U(0)) {
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return 0;
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}
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/*
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* FMU_ERR<M>STATUS.IERR indicates which Safety Mechanism
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* reported the error.
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*/
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ierr = (errstatus >> FMU_ERRSTATUS_IERR_SHIFT) &
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FMU_ERRSTATUS_IERR_MASK;
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/*
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* FMU_ERR<M>STATUS.SERR indicates architecturally
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* defined primary error code.
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*/
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serr = errstatus & FMU_ERRSTATUS_SERR_MASK;
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ERROR("**************************************\n");
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ERROR("RAS %s Error detected by GIC600 AE FMU\n",
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((errstatus & FMU_ERRSTATUS_UE_BIT) != 0U) ?
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"Uncorrectable" : "Corrected");
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ERROR("\tStatus = 0x%lx \n", errstatus);
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ERROR("\tBlock ID = 0x%x\n", blkid);
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ERROR("\tSafety Mechanism ID = 0x%x (%s)\n", ierr,
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ras_ierr_to_str(blkid, ierr));
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ERROR("\tArchitecturally defined primary error code = 0x%x\n",
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serr);
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ERROR("**************************************\n");
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/* Clear FMU_ERR<M>STATUS */
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gic_fmu_write_errstatus(base, probe_data, errstatus);
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return 0;
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}
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/*
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* Initialization sequence for the FMU
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*
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* 1. enable error detection for error records that are passed in the blk_present_mask
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* 2. enable MBIST REQ and FMU Clk Gate override safety mechanisms for error records
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* that are present on the platform
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*
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* The platforms are expected to pass `errctlr_ce_en` and `errctlr_ue_en`.
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*/
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void gic600_fmu_init(uint64_t base, uint64_t blk_present_mask,
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bool errctlr_ce_en, bool errctlr_ue_en)
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{
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unsigned int num_blk = gic_fmu_read_erridr(base) & FMU_ERRIDR_NUM_MASK;
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uint64_t errctlr;
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uint32_t smen;
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INFO("GIC600-AE FMU supports %d error records\n", num_blk);
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assert(num_blk == FMU_ERRIDR_NUM);
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/* sanitize block present mask */
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blk_present_mask &= FMU_BLK_PRESENT_MASK;
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/* Enable error detection for all error records */
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for (unsigned int i = 0U; i < num_blk; i++) {
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/* Skip next steps if the block is not present */
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if ((blk_present_mask & BIT(i)) == 0U) {
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continue;
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}
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/* Read the error record control register */
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errctlr = gic_fmu_read_errctlr(base, i);
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/* Enable error reporting and logging, if it is disabled */
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if ((errctlr & FMU_ERRCTLR_ED_BIT) == 0U) {
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errctlr |= FMU_ERRCTLR_ED_BIT;
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}
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/* Enable client provided ERRCTLR settings */
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errctlr |= (errctlr_ce_en ? (FMU_ERRCTLR_CI_BIT | FMU_ERRCTLR_CE_EN_BIT) : 0);
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errctlr |= (errctlr_ue_en ? FMU_ERRCTLR_UI_BIT : 0U);
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gic_fmu_write_errctlr(base, i, errctlr);
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}
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/*
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* Enable MBIST REQ error and FMU CLK gate override safety mechanisms for
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* all blocks
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*
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* GICD, SMID 23 and SMID 33
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* PPI, SMID 10 and SMID 12
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* ITS, SMID 13 and SMID 14
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*/
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if ((blk_present_mask & BIT(FMU_BLK_GICD)) != 0U) {
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smen = (GICD_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) |
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(FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT);
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gic_fmu_write_smen(base, smen);
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smen = (GICD_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) |
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(FMU_BLK_GICD << FMU_SMEN_BLK_SHIFT);
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gic_fmu_write_smen(base, smen);
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}
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for (unsigned int i = FMU_BLK_PPI0; i < FMU_BLK_PPI31; i++) {
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if ((blk_present_mask & BIT(i)) != 0U) {
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smen = (PPI_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) |
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(i << FMU_SMEN_BLK_SHIFT);
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gic_fmu_write_smen(base, smen);
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smen = (PPI_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) |
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(i << FMU_SMEN_BLK_SHIFT);
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gic_fmu_write_smen(base, smen);
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}
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}
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for (unsigned int i = FMU_BLK_ITS0; i < FMU_BLK_ITS7; i++) {
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if ((blk_present_mask & BIT(i)) != 0U) {
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smen = (ITS_MBIST_REQ_ERROR << FMU_SMEN_SMID_SHIFT) |
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(i << FMU_SMEN_BLK_SHIFT);
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gic_fmu_write_smen(base, smen);
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smen = (ITS_FMU_CLKGATE_ERROR << FMU_SMEN_SMID_SHIFT) |
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(i << FMU_SMEN_BLK_SHIFT);
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gic_fmu_write_smen(base, smen);
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}
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}
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}
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/*
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* This function enable the GICD background ping engine. The GICD sends ping
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* messages to each remote GIC block, and expects a PING_ACK back within the
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* specified timeout. Pings need to be enabled after programming the timeout
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* value.
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*/
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void gic600_fmu_enable_ping(uint64_t base, uint64_t blk_present_mask,
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unsigned int timeout_val, unsigned int interval_diff)
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{
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/*
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* Populate the PING Mask to skip a specific block while generating
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* background ping messages and enable the ping mechanism.
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*/
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gic_fmu_write_pingmask(base, ~blk_present_mask);
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gic_fmu_write_pingctlr(base, (interval_diff << FMU_PINGCTLR_INTDIFF_SHIFT) |
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(timeout_val << FMU_PINGCTLR_TIMEOUTVAL_SHIFT) | FMU_PINGCTLR_EN_BIT);
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}
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/* Print the safety mechanism description for a given block */
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void gic600_fmu_print_sm_info(uint64_t base, unsigned int blk, unsigned int smid)
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{
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if (blk == FMU_BLK_GICD && smid <= FMU_SMID_GICD_MAX) {
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INFO("GICD, SMID %d: %s\n", smid, gicd_sm_info[smid]);
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}
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if (blk == FMU_BLK_SPICOL && smid <= FMU_SMID_SPICOL_MAX) {
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INFO("SPI Collator, SMID %d: %s\n", smid, spicol_sm_info[smid]);
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}
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if (blk == FMU_BLK_WAKERQ && (smid <= FMU_SMID_WAKERQ_MAX)) {
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INFO("Wake Request, SMID %d: %s\n", smid, wkrqst_sm_info[smid]);
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}
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if (((blk >= FMU_BLK_ITS0) && (blk <= FMU_BLK_ITS7)) && (smid <= FMU_SMID_ITS_MAX)) {
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INFO("ITS, SMID %d: %s\n", smid, its_sm_info[smid]);
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}
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if (((blk >= FMU_BLK_PPI0) && (blk <= FMU_BLK_PPI31)) && (smid <= FMU_SMID_PPI_MAX)) {
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INFO("PPI, SMID %d: %s\n", smid, ppi_sm_info[smid]);
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}
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}
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