308dce4067
The GIC-600AE uses a range of RAS features for all RAMs, which include SECDED, ECC, and Scrub, software and bus error reporting. The GIC makes all necessary information available to software through Armv8.2 RAS architecture compliant register space. This patch introduces support to probe the FMU_ERRGSR register to find the right error record. Once the correct record is identified, the "handler" function queries the FMU_ERR<m>STATUS register to further identify the block ID, safety mechanism and the architecturally defined primary error code. The description of the error is displayed on the console to simplify debug. Change-Id: I7e543664b74457afee2da250549f4c3d9beb1a03 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> |
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