383 lines
12 KiB
C
383 lines
12 KiB
C
/*
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* Copyright (c) 2013, ARM Limited. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <console.h>
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#include <platform.h>
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#include <bl_common.h>
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#include <bl31.h>
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#include <bakery_lock.h>
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#include <cci400.h>
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#include <gic.h>
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#include <fvp_pwrc.h>
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/* Only included for error codes */
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#include <psci.h>
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/*******************************************************************************
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* FVP handler called when an affinity instance is about to be turned on. The
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* level and mpidr determine the affinity instance.
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******************************************************************************/
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int fvp_affinst_on(unsigned long mpidr,
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unsigned long sec_entrypoint,
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unsigned long ns_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned long linear_id;
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mailbox *fvp_mboxes;
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unsigned int psysr;
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if (ns_entrypoint < DRAM_BASE) {
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rc = PSCI_E_INVALID_PARAMS;
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goto exit;
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}
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/*
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* It's possible to turn on only affinity level 0 i.e. a cpu
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* on the FVP. Ignore any other affinity level.
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*/
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if (afflvl != MPIDR_AFFLVL0)
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goto exit;
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/*
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* Ensure that we do not cancel an inflight power off request
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* for the target cpu. That would leave it in a zombie wfi.
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* Wait for it to power off, program the jump address for the
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* target cpu and then program the power controller to turn
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* that cpu on
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*/
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do {
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psysr = fvp_pwrc_read_psysr(mpidr);
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} while (psysr & PSYSR_AFF_L0);
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
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fvp_mboxes[linear_id].value = sec_entrypoint;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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sizeof(unsigned long));
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fvp_pwrc_write_pponr(mpidr);
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exit:
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return rc;
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}
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/*******************************************************************************
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* FVP handler called when an affinity instance is about to be turned off. The
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* level and mpidr determine the affinity instance. The 'state' arg. allows the
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* platform to decide whether the cluster is being turned off and take apt
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* actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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******************************************************************************/
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int fvp_affinst_off(unsigned long mpidr,
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unsigned int afflvl,
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unsigned int state)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int gicc_base, ectlr;
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unsigned long cpu_setup, cci_setup;
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switch (afflvl) {
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case MPIDR_AFFLVL1:
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if (state == PSCI_STATE_OFF) {
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/*
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* Disable coherency if this cluster is to be
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* turned off
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*/
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_disable_coherency(mpidr);
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}
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/*
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* Program the power controller to turn the
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* cluster off
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*/
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fvp_pwrc_write_pcoffr(mpidr);
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}
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break;
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case MPIDR_AFFLVL0:
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if (state == PSCI_STATE_OFF) {
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/*
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* Take this cpu out of intra-cluster coherency if
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* the FVP flavour supports the SMP bit.
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*/
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cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
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if (cpu_setup) {
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ectlr = read_cpuectlr();
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ectlr &= ~CPUECTLR_SMP_BIT;
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write_cpuectlr(ectlr);
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}
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/*
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* Prevent interrupts from spuriously waking up
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* this cpu
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*/
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gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
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gic_cpuif_deactivate(gicc_base);
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/*
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* Program the power controller to power this
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* cpu off
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*/
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fvp_pwrc_write_ppoffr(mpidr);
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}
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break;
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default:
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assert(0);
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}
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return rc;
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}
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/*******************************************************************************
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* FVP handler called when an affinity instance is about to be suspended. The
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* level and mpidr determine the affinity instance. The 'state' arg. allows the
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* platform to decide whether the cluster is being turned off and take apt
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* actions.
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*
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* CAUTION: This function is called with coherent stacks so that caches can be
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* turned off, flushed and coherency disabled. There is no guarantee that caches
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* will remain turned on across calls to this function as each affinity level is
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* dealt with. So do not write & read global variables across calls. It will be
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* wise to do flush a write to the global to prevent unpredictable results.
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******************************************************************************/
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int fvp_affinst_suspend(unsigned long mpidr,
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unsigned long sec_entrypoint,
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unsigned long ns_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int gicc_base, ectlr;
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unsigned long cpu_setup, cci_setup, linear_id;
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mailbox *fvp_mboxes;
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/* Cannot allow NS world to execute trusted firmware code */
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if (ns_entrypoint < DRAM_BASE) {
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rc = PSCI_E_INVALID_PARAMS;
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goto exit;
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}
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switch (afflvl) {
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case MPIDR_AFFLVL1:
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if (state == PSCI_STATE_OFF) {
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/*
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* Disable coherency if this cluster is to be
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* turned off
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*/
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_disable_coherency(mpidr);
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}
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/*
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* Program the power controller to turn the
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* cluster off
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*/
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fvp_pwrc_write_pcoffr(mpidr);
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}
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break;
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case MPIDR_AFFLVL0:
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if (state == PSCI_STATE_OFF) {
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/*
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* Take this cpu out of intra-cluster coherency if
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* the FVP flavour supports the SMP bit.
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*/
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cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
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if (cpu_setup) {
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ectlr = read_cpuectlr();
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ectlr &= ~CPUECTLR_SMP_BIT;
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write_cpuectlr(ectlr);
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}
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/* Program the jump address for the target cpu */
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
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fvp_mboxes[linear_id].value = sec_entrypoint;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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sizeof(unsigned long));
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/*
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* Prevent interrupts from spuriously waking up
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* this cpu
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*/
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gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
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gic_cpuif_deactivate(gicc_base);
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/*
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* Program the power controller to power this
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* cpu off and enable wakeup interrupts.
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*/
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fvp_pwrc_write_pwkupr(mpidr);
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fvp_pwrc_write_ppoffr(mpidr);
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}
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break;
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default:
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assert(0);
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}
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exit:
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return rc;
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}
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/*******************************************************************************
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* FVP handler called when an affinity instance has just been powered on after
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* being turned off earlier. The level and mpidr determine the affinity
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* instance. The 'state' arg. allows the platform to decide whether the cluster
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* was turned off prior to wakeup and do what's necessary to setup it up
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* correctly.
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******************************************************************************/
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int fvp_affinst_on_finish(unsigned long mpidr,
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unsigned int afflvl,
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unsigned int state)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned long linear_id, cpu_setup, cci_setup;
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mailbox *fvp_mboxes;
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unsigned int gicd_base, gicc_base, reg_val, ectlr;
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switch (afflvl) {
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case MPIDR_AFFLVL1:
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/* Enable coherency if this cluster was off */
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if (state == PSCI_STATE_OFF) {
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cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
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if (cci_setup) {
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cci_enable_coherency(mpidr);
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}
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}
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break;
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case MPIDR_AFFLVL0:
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/*
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* Ignore the state passed for a cpu. It could only have
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* been off if we are here.
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*/
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/*
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* Turn on intra-cluster coherency if the FVP flavour supports
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* it.
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*/
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cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
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if (cpu_setup) {
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ectlr = read_cpuectlr();
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ectlr |= CPUECTLR_SMP_BIT;
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write_cpuectlr(ectlr);
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}
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/* Zero the jump address in the mailbox for this cpu */
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fvp_mboxes = (mailbox *) (TZDRAM_BASE + MBOX_OFF);
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linear_id = platform_get_core_pos(mpidr);
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fvp_mboxes[linear_id].value = 0;
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flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
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sizeof(unsigned long));
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gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
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gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
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/* Enable the gic cpu interface */
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gic_cpuif_setup(gicc_base);
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/* TODO: This setup is needed only after a cold boot */
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gic_pcpu_distif_setup(gicd_base);
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/* Allow access to the System counter timer module */
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reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
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reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
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reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
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mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
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mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
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reg_val = (1 << CNTNSAR_NS_SHIFT(0)) |
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(1 << CNTNSAR_NS_SHIFT(1));
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mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
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break;
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default:
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assert(0);
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}
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return rc;
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}
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/*******************************************************************************
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* FVP handler called when an affinity instance has just been powered on after
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* having been suspended earlier. The level and mpidr determine the affinity
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* instance.
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* TODO: At the moment we reuse the on finisher and reinitialize the secure
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* context. Need to implement a separate suspend finisher.
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******************************************************************************/
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int fvp_affinst_suspend_finish(unsigned long mpidr,
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unsigned int afflvl,
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unsigned int state)
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{
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return fvp_affinst_on_finish(mpidr, afflvl, state);
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}
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/*******************************************************************************
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* Export the platform handlers to enable psci to invoke them
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******************************************************************************/
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static plat_pm_ops fvp_plat_pm_ops = {
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0,
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fvp_affinst_on,
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fvp_affinst_off,
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fvp_affinst_suspend,
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fvp_affinst_on_finish,
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fvp_affinst_suspend_finish,
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};
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/*******************************************************************************
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* Export the platform specific power ops & initialize the fvp power controller
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******************************************************************************/
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int platform_setup_pm(plat_pm_ops **plat_ops)
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{
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*plat_ops = &fvp_plat_pm_ops;
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return 0;
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}
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